<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
  <files>
    <file id="a" filename="AstRoot" language="1800-2017"/>
    <file id="b" filename="COMMAND_LINE" language="1800-2017"/>
    <file id="e" filename="COMMAND_LINE_DEFINE" language="1800-2017"/>
    <file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2017"/>
    <file id="d" filename="input.vc" language="1800-2017"/>
    <file id="f" filename="t/t_xml_tag.v" language="1800-2017"/>
  </files>
  <module_files>
    <file id="f" filename="t/t_xml_tag.v" language="1800-2017"/>
  </module_files>
  <cells>
    <cell fl="f11" name="m" submodname="m" hier="m">
      <cell fl="f28" name="itop" submodname="ifc" hier="m.itop"/>
    </cell>
  </cells>
  <netlist>
    <module fl="f11" name="m" origName="m" topModule="1">
      <var fl="f13" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" vartype="logic" origName="clk_ip"/>
      <var fl="f14" name="rst_ip" dtype_id="1" dir="input" vartype="logic" origName="rst_ip"/>
      <var fl="f15" name="foo_op" tag="foo_op" dtype_id="1" dir="output" vartype="logic" origName="foo_op"/>
      <typedef fl="f19" name="my_struct" tag="my_struct" dtype_id="2"/>
      <instance fl="f28" name="itop" defName="ifc" origName="itop"/>
      <var fl="f28" name="itop__Viftop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>
      <var fl="f30" name="this_struct" tag="this_struct" dtype_id="4" vartype="" origName="this_struct"/>
      <var fl="f32" name="dotted" dtype_id="5" vartype="logic" origName="dotted"/>
      <contassign fl="f32" dtype_id="5">
        <varxref fl="f32" name="value" dtype_id="6" dotted="itop"/>
        <varref fl="f32" name="dotted" dtype_id="5"/>
      </contassign>
    </module>
    <iface fl="f6" name="ifc" origName="ifc">
      <var fl="f7" name="value" dtype_id="6" vartype="integer" origName="value"/>
      <modport fl="f8" name="out_modport">
        <modportvarref fl="f8" name="value" direction="out"/>
      </modport>
    </iface>
    <typetable fl="a0">
      <basicdtype  fl="f30" id="5" name="logic" left="31" right="0"/>
      <basicdtype  fl="f7" id="6" name="integer" left="31" right="0"/>
      <basicdtype  fl="f13" id="1" name="logic"/>
      <structdtype fl="f19" id="2" name="m.my_struct">
        <memberdtype fl="f20" id="7" name="clk" tag="this is clk" sub_dtype_id="8"/>
        <memberdtype fl="f21" id="9" name="k" sub_dtype_id="10"/>
        <memberdtype fl="f22" id="11" name="enable" tag="enable" sub_dtype_id="12"/>
        <memberdtype fl="f23" id="13" name="data" tag="data" sub_dtype_id="14"/>
      </structdtype>
      <basicdtype  fl="f20" id="8" name="logic"/>
      <basicdtype  fl="f21" id="10" name="logic"/>
      <basicdtype  fl="f22" id="12" name="logic"/>
      <basicdtype  fl="f23" id="14" name="logic"/>
      <ifacerefdtype fl="f28" id="3" modportname=""/>
      <unpackarraydtype fl="f30" id="4" sub_dtype_id="2">
        <range fl="f30">
          <const fl="f30" name="32'h1" dtype_id="5"/>
          <const fl="f30" name="32'h0" dtype_id="5"/>
        </range>
      </unpackarraydtype>
      <refdtype fl="f30" id="15" name="my_struct" sub_dtype_id="2"/>
    </typetable>
  </netlist>
</verilator_xml>
