<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
  <files>
    <file id="a" filename="AstRoot" language="1800-2017"/>
    <file id="b" filename="COMMAND_LINE" language="1800-2017"/>
    <file id="e" filename="COMMAND_LINE_DEFINE" language="1800-2017"/>
    <file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2017"/>
    <file id="d" filename="input.vc" language="1800-2017"/>
    <file id="f" filename="t/t_xml_first.v" language="1800-2017"/>
  </files>
  <module_files>
    <file id="f" filename="t/t_xml_first.v" language="1800-2017"/>
  </module_files>
  <cells>
    <cell fl="f6" name="t" submodname="t" hier="t">
      <cell fl="f18" name="cell1" submodname="mod1" hier="t.cell1"/>
      <cell fl="f24" name="cell2" submodname="mod2" hier="t.cell2"/>
    </cell>
  </cells>
  <netlist>
    <module fl="f6" name="t" origName="t" topModule="1">
      <var fl="f12" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
      <var fl="f13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
      <var fl="f14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
      <var fl="f16" name="between" dtype_id="2" vartype="logic" origName="between"/>
      <instance fl="f18" name="cell1" defName="mod1" origName="cell1">
        <port fl="f18" name="q" direction="out" portIndex="1">
          <varref fl="f18" name="between" dtype_id="2"/>
        </port>
        <port fl="f21" name="clk" direction="in" portIndex="2">
          <varref fl="f21" name="clk" dtype_id="1"/>
        </port>
        <port fl="f22" name="d" direction="in" portIndex="3">
          <varref fl="f22" name="d" dtype_id="2"/>
        </port>
      </instance>
      <instance fl="f24" name="cell2" defName="mod2" origName="cell2">
        <port fl="f24" name="d" direction="in" portIndex="1">
          <varref fl="f24" name="between" dtype_id="2"/>
        </port>
        <port fl="f27" name="q" direction="out" portIndex="2">
          <varref fl="f27" name="q" dtype_id="2"/>
        </port>
        <port fl="f29" name="clk" direction="in" portIndex="3">
          <varref fl="f29" name="clk" dtype_id="1"/>
        </port>
      </instance>
    </module>
    <module fl="f33" name="mod1" origName="mod1">
      <var fl="f35" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
      <var fl="f36" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
      <var fl="f37" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
      <always fl="f39">
        <sentree fl="f39">
          <senitem fl="f39" edgeType="POS">
            <varref fl="f39" name="clk" dtype_id="1"/>
          </senitem>
        </sentree>
        <assigndly fl="f40" dtype_id="2">
          <varref fl="f40" name="d" dtype_id="2"/>
          <varref fl="f40" name="q" dtype_id="2"/>
        </assigndly>
      </always>
    </module>
    <module fl="f44" name="mod2" origName="mod2">
      <var fl="f46" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
      <var fl="f47" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
      <var fl="f48" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
      <contassign fl="f51" dtype_id="2">
        <varref fl="f51" name="d" dtype_id="2"/>
        <varref fl="f51" name="q" dtype_id="2"/>
      </contassign>
    </module>
    <typetable fl="a0">
      <basicdtype  fl="f46" id="1" name="logic"/>
      <basicdtype  fl="f13" id="2" name="logic" left="3" right="0"/>
    </typetable>
  </netlist>
</verilator_xml>
