/*
* File:    power9_events.h
* CVS:
* Author:  Will Schmidt
*          will_schmidt@vnet.ibm.com
* Author:  Carl Love
*          cel@us.ibm.com
*
* Mods:
* Initial content generated by Will Schmidt.  (Jan 31, 2017).
* Refresh/update generated Jun 06, 2017 by Will Schmidt.
* missing _ALT events added, Nov 16, 2017 by Will Schmidt.
*
* Contributed by
* (C) Copyright IBM Corporation, 2017.  All Rights Reserved.
*
* Note: This code was automatically generated and should not be modified by
* hand.
*
* Documentation on the PMU events will be published at:
*  ...
*/

#ifndef __POWER9_EVENTS_H__
#define __POWER9_EVENTS_H__

#define POWER9_PME_PM_1FLOP_CMPL 0
#define POWER9_PME_PM_1PLUS_PPC_CMPL 1
#define POWER9_PME_PM_1PLUS_PPC_DISP 2
#define POWER9_PME_PM_2FLOP_CMPL 3
#define POWER9_PME_PM_4FLOP_CMPL 4
#define POWER9_PME_PM_8FLOP_CMPL 5
#define POWER9_PME_PM_ANY_THRD_RUN_CYC 6
#define POWER9_PME_PM_BACK_BR_CMPL 7
#define POWER9_PME_PM_BANK_CONFLICT 8
#define POWER9_PME_PM_BFU_BUSY 9
#define POWER9_PME_PM_BR_2PATH 10
#define POWER9_PME_PM_BR_CMPL 11
#define POWER9_PME_PM_BR_CORECT_PRED_TAKEN_CMPL 12
#define POWER9_PME_PM_BR_MPRED_CCACHE 13
#define POWER9_PME_PM_BR_MPRED_CMPL 14
#define POWER9_PME_PM_BR_MPRED_LSTACK 15
#define POWER9_PME_PM_BR_MPRED_PCACHE 16
#define POWER9_PME_PM_BR_MPRED_TAKEN_CR 17
#define POWER9_PME_PM_BR_MPRED_TAKEN_TA 18
#define POWER9_PME_PM_BR_PRED_CCACHE 19
#define POWER9_PME_PM_BR_PRED_LSTACK 20
#define POWER9_PME_PM_BR_PRED_PCACHE 21
#define POWER9_PME_PM_BR_PRED_TAKEN_CR 22
#define POWER9_PME_PM_BR_PRED_TA 23
#define POWER9_PME_PM_BR_PRED 24
#define POWER9_PME_PM_BR_TAKEN_CMPL 25
#define POWER9_PME_PM_BRU_FIN 26
#define POWER9_PME_PM_BR_UNCOND 27
#define POWER9_PME_PM_BTAC_BAD_RESULT 28
#define POWER9_PME_PM_BTAC_GOOD_RESULT 29
#define POWER9_PME_PM_CHIP_PUMP_CPRED 30
#define POWER9_PME_PM_CLB_HELD 31
#define POWER9_PME_PM_CMPLU_STALL_ANY_SYNC 32
#define POWER9_PME_PM_CMPLU_STALL_BRU 33
#define POWER9_PME_PM_CMPLU_STALL_CRYPTO 34
#define POWER9_PME_PM_CMPLU_STALL_DCACHE_MISS 35
#define POWER9_PME_PM_CMPLU_STALL_DFLONG 36
#define POWER9_PME_PM_CMPLU_STALL_DFU 37
#define POWER9_PME_PM_CMPLU_STALL_DMISS_L21_L31 38
#define POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT 39
#define POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3 40
#define POWER9_PME_PM_CMPLU_STALL_DMISS_L3MISS 41
#define POWER9_PME_PM_CMPLU_STALL_DMISS_LMEM 42
#define POWER9_PME_PM_CMPLU_STALL_DMISS_REMOTE 43
#define POWER9_PME_PM_CMPLU_STALL_DPLONG 44
#define POWER9_PME_PM_CMPLU_STALL_DP 45
#define POWER9_PME_PM_CMPLU_STALL_EIEIO 46
#define POWER9_PME_PM_CMPLU_STALL_EMQ_FULL 47
#define POWER9_PME_PM_CMPLU_STALL_ERAT_MISS 48
#define POWER9_PME_PM_CMPLU_STALL_EXCEPTION 49
#define POWER9_PME_PM_CMPLU_STALL_EXEC_UNIT 50
#define POWER9_PME_PM_CMPLU_STALL_FLUSH_ANY_THREAD 51
#define POWER9_PME_PM_CMPLU_STALL_FXLONG 52
#define POWER9_PME_PM_CMPLU_STALL_FXU 53
#define POWER9_PME_PM_CMPLU_STALL_HWSYNC 54
#define POWER9_PME_PM_CMPLU_STALL_LARX 55
#define POWER9_PME_PM_CMPLU_STALL_LHS 56
#define POWER9_PME_PM_CMPLU_STALL_LMQ_FULL 57
#define POWER9_PME_PM_CMPLU_STALL_LOAD_FINISH 58
#define POWER9_PME_PM_CMPLU_STALL_LRQ_FULL 59
#define POWER9_PME_PM_CMPLU_STALL_LRQ_OTHER 60
#define POWER9_PME_PM_CMPLU_STALL_LSAQ_ARB 61
#define POWER9_PME_PM_CMPLU_STALL_LSU_FIN 62
#define POWER9_PME_PM_CMPLU_STALL_LSU_FLUSH_NEXT 63
#define POWER9_PME_PM_CMPLU_STALL_LSU_MFSPR 64
#define POWER9_PME_PM_CMPLU_STALL_LSU 65
#define POWER9_PME_PM_CMPLU_STALL_LWSYNC 66
#define POWER9_PME_PM_CMPLU_STALL_MTFPSCR 67
#define POWER9_PME_PM_CMPLU_STALL_NESTED_TBEGIN 68
#define POWER9_PME_PM_CMPLU_STALL_NESTED_TEND 69
#define POWER9_PME_PM_CMPLU_STALL_NTC_DISP_FIN 70
#define POWER9_PME_PM_CMPLU_STALL_NTC_FLUSH 71
#define POWER9_PME_PM_CMPLU_STALL_OTHER_CMPL 72
#define POWER9_PME_PM_CMPLU_STALL_PASTE 73
#define POWER9_PME_PM_CMPLU_STALL_PM 74
#define POWER9_PME_PM_CMPLU_STALL_SLB 75
#define POWER9_PME_PM_CMPLU_STALL_SPEC_FINISH 76
#define POWER9_PME_PM_CMPLU_STALL_SRQ_FULL 77
#define POWER9_PME_PM_CMPLU_STALL_STCX 78
#define POWER9_PME_PM_CMPLU_STALL_ST_FWD 79
#define POWER9_PME_PM_CMPLU_STALL_STORE_DATA 80
#define POWER9_PME_PM_CMPLU_STALL_STORE_FIN_ARB 81
#define POWER9_PME_PM_CMPLU_STALL_STORE_FINISH 82
#define POWER9_PME_PM_CMPLU_STALL_STORE_PIPE_ARB 83
#define POWER9_PME_PM_CMPLU_STALL_SYNC_PMU_INT 84
#define POWER9_PME_PM_CMPLU_STALL_TEND 85
#define POWER9_PME_PM_CMPLU_STALL_THRD 86
#define POWER9_PME_PM_CMPLU_STALL_TLBIE 87
#define POWER9_PME_PM_CMPLU_STALL 88
#define POWER9_PME_PM_CMPLU_STALL_VDPLONG 89
#define POWER9_PME_PM_CMPLU_STALL_VDP 90
#define POWER9_PME_PM_CMPLU_STALL_VFXLONG 91
#define POWER9_PME_PM_CMPLU_STALL_VFXU 92
#define POWER9_PME_PM_CO0_BUSY 93
#define POWER9_PME_PM_CO0_BUSY_ALT 94
#define POWER9_PME_PM_CO_DISP_FAIL 95
#define POWER9_PME_PM_CO_TM_SC_FOOTPRINT 96
#define POWER9_PME_PM_CO_USAGE 97
#define POWER9_PME_PM_CYC 98
#define POWER9_PME_PM_DARQ0_0_3_ENTRIES 99
#define POWER9_PME_PM_DARQ0_10_12_ENTRIES 100
#define POWER9_PME_PM_DARQ0_4_6_ENTRIES 101
#define POWER9_PME_PM_DARQ0_7_9_ENTRIES 102
#define POWER9_PME_PM_DARQ1_0_3_ENTRIES 103
#define POWER9_PME_PM_DARQ1_10_12_ENTRIES 104
#define POWER9_PME_PM_DARQ1_4_6_ENTRIES 105
#define POWER9_PME_PM_DARQ1_7_9_ENTRIES 106
#define POWER9_PME_PM_DARQ_STORE_REJECT 107
#define POWER9_PME_PM_DARQ_STORE_XMIT 108
#define POWER9_PME_PM_DATA_CHIP_PUMP_CPRED 109
#define POWER9_PME_PM_DATA_FROM_DL2L3_MOD 110
#define POWER9_PME_PM_DATA_FROM_DL2L3_SHR 111
#define POWER9_PME_PM_DATA_FROM_DL4 112
#define POWER9_PME_PM_DATA_FROM_DMEM 113
#define POWER9_PME_PM_DATA_FROM_L21_MOD 114
#define POWER9_PME_PM_DATA_FROM_L21_SHR 115
#define POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST 116
#define POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER 117
#define POWER9_PME_PM_DATA_FROM_L2_MEPF 118
#define POWER9_PME_PM_DATA_FROM_L2MISS_MOD 119
#define POWER9_PME_PM_DATA_FROM_L2MISS 120
#define POWER9_PME_PM_DATA_FROM_L2_NO_CONFLICT 121
#define POWER9_PME_PM_DATA_FROM_L2 122
#define POWER9_PME_PM_DATA_FROM_L31_ECO_MOD 123
#define POWER9_PME_PM_DATA_FROM_L31_ECO_SHR 124
#define POWER9_PME_PM_DATA_FROM_L31_MOD 125
#define POWER9_PME_PM_DATA_FROM_L31_SHR 126
#define POWER9_PME_PM_DATA_FROM_L3_DISP_CONFLICT 127
#define POWER9_PME_PM_DATA_FROM_L3_MEPF 128
#define POWER9_PME_PM_DATA_FROM_L3MISS_MOD 129
#define POWER9_PME_PM_DATA_FROM_L3MISS 130
#define POWER9_PME_PM_DATA_FROM_L3_NO_CONFLICT 131
#define POWER9_PME_PM_DATA_FROM_L3 132
#define POWER9_PME_PM_DATA_FROM_LL4 133
#define POWER9_PME_PM_DATA_FROM_LMEM 134
#define POWER9_PME_PM_DATA_FROM_MEMORY 135
#define POWER9_PME_PM_DATA_FROM_OFF_CHIP_CACHE 136
#define POWER9_PME_PM_DATA_FROM_ON_CHIP_CACHE 137
#define POWER9_PME_PM_DATA_FROM_RL2L3_MOD 138
#define POWER9_PME_PM_DATA_FROM_RL2L3_SHR 139
#define POWER9_PME_PM_DATA_FROM_RL4 140
#define POWER9_PME_PM_DATA_FROM_RMEM 141
#define POWER9_PME_PM_DATA_GRP_PUMP_CPRED 142
#define POWER9_PME_PM_DATA_GRP_PUMP_MPRED_RTY 143
#define POWER9_PME_PM_DATA_GRP_PUMP_MPRED 144
#define POWER9_PME_PM_DATA_PUMP_CPRED 145
#define POWER9_PME_PM_DATA_PUMP_MPRED 146
#define POWER9_PME_PM_DATA_STORE 147
#define POWER9_PME_PM_DATA_SYS_PUMP_CPRED 148
#define POWER9_PME_PM_DATA_SYS_PUMP_MPRED_RTY 149
#define POWER9_PME_PM_DATA_SYS_PUMP_MPRED 150
#define POWER9_PME_PM_DATA_TABLEWALK_CYC 151
#define POWER9_PME_PM_DC_DEALLOC_NO_CONF 152
#define POWER9_PME_PM_DC_PREF_CONF 153
#define POWER9_PME_PM_DC_PREF_CONS_ALLOC 154
#define POWER9_PME_PM_DC_PREF_FUZZY_CONF 155
#define POWER9_PME_PM_DC_PREF_HW_ALLOC 156
#define POWER9_PME_PM_DC_PREF_STRIDED_CONF 157
#define POWER9_PME_PM_DC_PREF_SW_ALLOC 158
#define POWER9_PME_PM_DC_PREF_XCONS_ALLOC 159
#define POWER9_PME_PM_DECODE_FUSION_CONST_GEN 160
#define POWER9_PME_PM_DECODE_FUSION_EXT_ADD 161
#define POWER9_PME_PM_DECODE_FUSION_LD_ST_DISP 162
#define POWER9_PME_PM_DECODE_FUSION_OP_PRESERV 163
#define POWER9_PME_PM_DECODE_HOLD_ICT_FULL 164
#define POWER9_PME_PM_DECODE_LANES_NOT_AVAIL 165
#define POWER9_PME_PM_DERAT_MISS_16G 166
#define POWER9_PME_PM_DERAT_MISS_16M 167
#define POWER9_PME_PM_DERAT_MISS_1G 168
#define POWER9_PME_PM_DERAT_MISS_2M 169
#define POWER9_PME_PM_DERAT_MISS_4K 170
#define POWER9_PME_PM_DERAT_MISS_64K 171
#define POWER9_PME_PM_DFU_BUSY 172
#define POWER9_PME_PM_DISP_CLB_HELD_BAL 173
#define POWER9_PME_PM_DISP_CLB_HELD_SB 174
#define POWER9_PME_PM_DISP_CLB_HELD_TLBIE 175
#define POWER9_PME_PM_DISP_HELD_HB_FULL 176
#define POWER9_PME_PM_DISP_HELD_ISSQ_FULL 177
#define POWER9_PME_PM_DISP_HELD_SYNC_HOLD 178
#define POWER9_PME_PM_DISP_HELD_TBEGIN 179
#define POWER9_PME_PM_DISP_HELD 180
#define POWER9_PME_PM_DISP_STARVED 181
#define POWER9_PME_PM_DP_QP_FLOP_CMPL 182
#define POWER9_PME_PM_DPTEG_FROM_DL2L3_MOD 183
#define POWER9_PME_PM_DPTEG_FROM_DL2L3_SHR 184
#define POWER9_PME_PM_DPTEG_FROM_DL4 185
#define POWER9_PME_PM_DPTEG_FROM_DMEM 186
#define POWER9_PME_PM_DPTEG_FROM_L21_MOD 187
#define POWER9_PME_PM_DPTEG_FROM_L21_SHR 188
#define POWER9_PME_PM_DPTEG_FROM_L2_MEPF 189
#define POWER9_PME_PM_DPTEG_FROM_L2MISS 190
#define POWER9_PME_PM_DPTEG_FROM_L2_NO_CONFLICT 191
#define POWER9_PME_PM_DPTEG_FROM_L2 192
#define POWER9_PME_PM_DPTEG_FROM_L31_ECO_MOD 193
#define POWER9_PME_PM_DPTEG_FROM_L31_ECO_SHR 194
#define POWER9_PME_PM_DPTEG_FROM_L31_MOD 195
#define POWER9_PME_PM_DPTEG_FROM_L31_SHR 196
#define POWER9_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT 197
#define POWER9_PME_PM_DPTEG_FROM_L3_MEPF 198
#define POWER9_PME_PM_DPTEG_FROM_L3MISS 199
#define POWER9_PME_PM_DPTEG_FROM_L3_NO_CONFLICT 200
#define POWER9_PME_PM_DPTEG_FROM_L3 201
#define POWER9_PME_PM_DPTEG_FROM_LL4 202
#define POWER9_PME_PM_DPTEG_FROM_LMEM 203
#define POWER9_PME_PM_DPTEG_FROM_MEMORY 204
#define POWER9_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE 205
#define POWER9_PME_PM_DPTEG_FROM_ON_CHIP_CACHE 206
#define POWER9_PME_PM_DPTEG_FROM_RL2L3_MOD 207
#define POWER9_PME_PM_DPTEG_FROM_RL2L3_SHR 208
#define POWER9_PME_PM_DPTEG_FROM_RL4 209
#define POWER9_PME_PM_DPTEG_FROM_RMEM 210
#define POWER9_PME_PM_DSIDE_L2MEMACC 211
#define POWER9_PME_PM_DSIDE_MRU_TOUCH 212
#define POWER9_PME_PM_DSIDE_OTHER_64B_L2MEMACC 213
#define POWER9_PME_PM_DSLB_MISS 214
#define POWER9_PME_PM_DSLB_MISS_ALT 215
#define POWER9_PME_PM_DTLB_MISS_16G 216
#define POWER9_PME_PM_DTLB_MISS_16M 217
#define POWER9_PME_PM_DTLB_MISS_1G 218
#define POWER9_PME_PM_DTLB_MISS_2M 219
#define POWER9_PME_PM_DTLB_MISS_4K 220
#define POWER9_PME_PM_DTLB_MISS_64K 221
#define POWER9_PME_PM_DTLB_MISS 222
#define POWER9_PME_PM_SPACEHOLDER_0000040062 223
#define POWER9_PME_PM_SPACEHOLDER_0000040064 224
#define POWER9_PME_PM_EAT_FORCE_MISPRED 225
#define POWER9_PME_PM_EAT_FULL_CYC 226
#define POWER9_PME_PM_EE_OFF_EXT_INT 227
#define POWER9_PME_PM_EXT_INT 228
#define POWER9_PME_PM_FLOP_CMPL 229
#define POWER9_PME_PM_FLUSH_COMPLETION 230
#define POWER9_PME_PM_FLUSH_DISP_SB 231
#define POWER9_PME_PM_FLUSH_DISP_TLBIE 232
#define POWER9_PME_PM_FLUSH_DISP 233
#define POWER9_PME_PM_FLUSH_HB_RESTORE_CYC 234
#define POWER9_PME_PM_FLUSH_LSU 235
#define POWER9_PME_PM_FLUSH_MPRED 236
#define POWER9_PME_PM_FLUSH 237
#define POWER9_PME_PM_FMA_CMPL 238
#define POWER9_PME_PM_FORCED_NOP 239
#define POWER9_PME_PM_FREQ_DOWN 240
#define POWER9_PME_PM_FREQ_UP 241
#define POWER9_PME_PM_FXU_1PLUS_BUSY 242
#define POWER9_PME_PM_FXU_BUSY 243
#define POWER9_PME_PM_FXU_FIN 244
#define POWER9_PME_PM_FXU_IDLE 245
#define POWER9_PME_PM_GRP_PUMP_CPRED 246
#define POWER9_PME_PM_GRP_PUMP_MPRED_RTY 247
#define POWER9_PME_PM_GRP_PUMP_MPRED 248
#define POWER9_PME_PM_HV_CYC 249
#define POWER9_PME_PM_HWSYNC 250
#define POWER9_PME_PM_IBUF_FULL_CYC 251
#define POWER9_PME_PM_IC_DEMAND_CYC 252
#define POWER9_PME_PM_IC_DEMAND_L2_BHT_REDIRECT 253
#define POWER9_PME_PM_IC_DEMAND_L2_BR_REDIRECT 254
#define POWER9_PME_PM_IC_DEMAND_REQ 255
#define POWER9_PME_PM_IC_INVALIDATE 256
#define POWER9_PME_PM_IC_MISS_CMPL 257
#define POWER9_PME_PM_IC_MISS_ICBI 258
#define POWER9_PME_PM_IC_PREF_CANCEL_HIT 259
#define POWER9_PME_PM_IC_PREF_CANCEL_L2 260
#define POWER9_PME_PM_IC_PREF_CANCEL_PAGE 261
#define POWER9_PME_PM_IC_PREF_REQ 262
#define POWER9_PME_PM_IC_PREF_WRITE 263
#define POWER9_PME_PM_IC_RELOAD_PRIVATE 264
#define POWER9_PME_PM_ICT_EMPTY_CYC 265
#define POWER9_PME_PM_ICT_NOSLOT_BR_MPRED_ICMISS 266
#define POWER9_PME_PM_ICT_NOSLOT_BR_MPRED 267
#define POWER9_PME_PM_ICT_NOSLOT_CYC 268
#define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_HB_FULL 269
#define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_ISSQ 270
#define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_SYNC 271
#define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_TBEGIN 272
#define POWER9_PME_PM_ICT_NOSLOT_DISP_HELD 273
#define POWER9_PME_PM_ICT_NOSLOT_IC_L3MISS 274
#define POWER9_PME_PM_ICT_NOSLOT_IC_L3 275
#define POWER9_PME_PM_ICT_NOSLOT_IC_MISS 276
#define POWER9_PME_PM_IERAT_RELOAD_16M 277
#define POWER9_PME_PM_IERAT_RELOAD_4K 278
#define POWER9_PME_PM_IERAT_RELOAD_64K 279
#define POWER9_PME_PM_IERAT_RELOAD 280
#define POWER9_PME_PM_IFETCH_THROTTLE 281
#define POWER9_PME_PM_INST_CHIP_PUMP_CPRED 282
#define POWER9_PME_PM_INST_CMPL 283
#define POWER9_PME_PM_INST_DISP 284
#define POWER9_PME_PM_INST_FROM_DL2L3_MOD 285
#define POWER9_PME_PM_INST_FROM_DL2L3_SHR 286
#define POWER9_PME_PM_INST_FROM_DL4 287
#define POWER9_PME_PM_INST_FROM_DMEM 288
#define POWER9_PME_PM_INST_FROM_L1 289
#define POWER9_PME_PM_INST_FROM_L21_MOD 290
#define POWER9_PME_PM_INST_FROM_L21_SHR 291
#define POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST 292
#define POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER 293
#define POWER9_PME_PM_INST_FROM_L2_MEPF 294
#define POWER9_PME_PM_INST_FROM_L2MISS 295
#define POWER9_PME_PM_INST_FROM_L2_NO_CONFLICT 296
#define POWER9_PME_PM_INST_FROM_L2 297
#define POWER9_PME_PM_INST_FROM_L31_ECO_MOD 298
#define POWER9_PME_PM_INST_FROM_L31_ECO_SHR 299
#define POWER9_PME_PM_INST_FROM_L31_MOD 300
#define POWER9_PME_PM_INST_FROM_L31_SHR 301
#define POWER9_PME_PM_INST_FROM_L3_DISP_CONFLICT 302
#define POWER9_PME_PM_INST_FROM_L3_MEPF 303
#define POWER9_PME_PM_INST_FROM_L3MISS_MOD 304
#define POWER9_PME_PM_INST_FROM_L3MISS 305
#define POWER9_PME_PM_INST_FROM_L3_NO_CONFLICT 306
#define POWER9_PME_PM_INST_FROM_L3 307
#define POWER9_PME_PM_INST_FROM_LL4 308
#define POWER9_PME_PM_INST_FROM_LMEM 309
#define POWER9_PME_PM_INST_FROM_MEMORY 310
#define POWER9_PME_PM_INST_FROM_OFF_CHIP_CACHE 311
#define POWER9_PME_PM_INST_FROM_ON_CHIP_CACHE 312
#define POWER9_PME_PM_INST_FROM_RL2L3_MOD 313
#define POWER9_PME_PM_INST_FROM_RL2L3_SHR 314
#define POWER9_PME_PM_INST_FROM_RL4 315
#define POWER9_PME_PM_INST_FROM_RMEM 316
#define POWER9_PME_PM_INST_GRP_PUMP_CPRED 317
#define POWER9_PME_PM_INST_GRP_PUMP_MPRED_RTY 318
#define POWER9_PME_PM_INST_GRP_PUMP_MPRED 319
#define POWER9_PME_PM_INST_IMC_MATCH_CMPL 320
#define POWER9_PME_PM_INST_PUMP_CPRED 321
#define POWER9_PME_PM_INST_PUMP_MPRED 322
#define POWER9_PME_PM_INST_SYS_PUMP_CPRED 323
#define POWER9_PME_PM_INST_SYS_PUMP_MPRED_RTY 324
#define POWER9_PME_PM_INST_SYS_PUMP_MPRED 325
#define POWER9_PME_PM_IOPS_CMPL 326
#define POWER9_PME_PM_IPTEG_FROM_DL2L3_MOD 327
#define POWER9_PME_PM_IPTEG_FROM_DL2L3_SHR 328
#define POWER9_PME_PM_IPTEG_FROM_DL4 329
#define POWER9_PME_PM_IPTEG_FROM_DMEM 330
#define POWER9_PME_PM_IPTEG_FROM_L21_MOD 331
#define POWER9_PME_PM_IPTEG_FROM_L21_SHR 332
#define POWER9_PME_PM_IPTEG_FROM_L2_MEPF 333
#define POWER9_PME_PM_IPTEG_FROM_L2MISS 334
#define POWER9_PME_PM_IPTEG_FROM_L2_NO_CONFLICT 335
#define POWER9_PME_PM_IPTEG_FROM_L2 336
#define POWER9_PME_PM_IPTEG_FROM_L31_ECO_MOD 337
#define POWER9_PME_PM_IPTEG_FROM_L31_ECO_SHR 338
#define POWER9_PME_PM_IPTEG_FROM_L31_MOD 339
#define POWER9_PME_PM_IPTEG_FROM_L31_SHR 340
#define POWER9_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT 341
#define POWER9_PME_PM_IPTEG_FROM_L3_MEPF 342
#define POWER9_PME_PM_IPTEG_FROM_L3MISS 343
#define POWER9_PME_PM_IPTEG_FROM_L3_NO_CONFLICT 344
#define POWER9_PME_PM_IPTEG_FROM_L3 345
#define POWER9_PME_PM_IPTEG_FROM_LL4 346
#define POWER9_PME_PM_IPTEG_FROM_LMEM 347
#define POWER9_PME_PM_IPTEG_FROM_MEMORY 348
#define POWER9_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE 349
#define POWER9_PME_PM_IPTEG_FROM_ON_CHIP_CACHE 350
#define POWER9_PME_PM_IPTEG_FROM_RL2L3_MOD 351
#define POWER9_PME_PM_IPTEG_FROM_RL2L3_SHR 352
#define POWER9_PME_PM_IPTEG_FROM_RL4 353
#define POWER9_PME_PM_IPTEG_FROM_RMEM 354
#define POWER9_PME_PM_ISIDE_DISP_FAIL_ADDR 355
#define POWER9_PME_PM_ISIDE_DISP_FAIL_OTHER 356
#define POWER9_PME_PM_ISIDE_DISP 357
#define POWER9_PME_PM_ISIDE_L2MEMACC 358
#define POWER9_PME_PM_ISIDE_MRU_TOUCH 359
#define POWER9_PME_PM_ISLB_MISS 360
#define POWER9_PME_PM_ISLB_MISS_ALT 361
#define POWER9_PME_PM_ISQ_0_8_ENTRIES 362
#define POWER9_PME_PM_ISQ_36_44_ENTRIES 363
#define POWER9_PME_PM_ISU0_ISS_HOLD_ALL 364
#define POWER9_PME_PM_ISU1_ISS_HOLD_ALL 365
#define POWER9_PME_PM_ISU2_ISS_HOLD_ALL 366
#define POWER9_PME_PM_ISU3_ISS_HOLD_ALL 367
#define POWER9_PME_PM_ISYNC 368
#define POWER9_PME_PM_ITLB_MISS 369
#define POWER9_PME_PM_L1_DCACHE_RELOADED_ALL 370
#define POWER9_PME_PM_L1_DCACHE_RELOAD_VALID 371
#define POWER9_PME_PM_L1_DEMAND_WRITE 372
#define POWER9_PME_PM_L1_ICACHE_MISS 373
#define POWER9_PME_PM_L1_ICACHE_RELOADED_ALL 374
#define POWER9_PME_PM_L1_ICACHE_RELOADED_PREF 375
#define POWER9_PME_PM_L1PF_L2MEMACC 376
#define POWER9_PME_PM_L1_PREF 377
#define POWER9_PME_PM_L1_SW_PREF 378
#define POWER9_PME_PM_L2_CASTOUT_MOD 379
#define POWER9_PME_PM_L2_CASTOUT_SHR 380
#define POWER9_PME_PM_L2_CHIP_PUMP 381
#define POWER9_PME_PM_L2_DC_INV 382
#define POWER9_PME_PM_L2_DISP_ALL_L2MISS 383
#define POWER9_PME_PM_L2_GROUP_PUMP 384
#define POWER9_PME_PM_L2_GRP_GUESS_CORRECT 385
#define POWER9_PME_PM_L2_GRP_GUESS_WRONG 386
#define POWER9_PME_PM_L2_IC_INV 387
#define POWER9_PME_PM_L2_INST_MISS 388
#define POWER9_PME_PM_L2_INST_MISS_ALT 389
#define POWER9_PME_PM_L2_INST 390
#define POWER9_PME_PM_L2_INST_ALT 391
#define POWER9_PME_PM_L2_LD_DISP 392
#define POWER9_PME_PM_L2_LD_DISP_ALT 393
#define POWER9_PME_PM_L2_LD_HIT 394
#define POWER9_PME_PM_L2_LD_HIT_ALT 395
#define POWER9_PME_PM_L2_LD_MISS_128B 396
#define POWER9_PME_PM_L2_LD_MISS_64B 397
#define POWER9_PME_PM_L2_LD_MISS 398
#define POWER9_PME_PM_L2_LD 399
#define POWER9_PME_PM_L2_LOC_GUESS_CORRECT 400
#define POWER9_PME_PM_L2_LOC_GUESS_WRONG 401
#define POWER9_PME_PM_L2_RCLD_DISP_FAIL_ADDR 402
#define POWER9_PME_PM_L2_RCLD_DISP_FAIL_OTHER 403
#define POWER9_PME_PM_L2_RCLD_DISP 404
#define POWER9_PME_PM_L2_RCST_DISP_FAIL_ADDR 405
#define POWER9_PME_PM_L2_RCST_DISP_FAIL_OTHER 406
#define POWER9_PME_PM_L2_RCST_DISP 407
#define POWER9_PME_PM_L2_RC_ST_DONE 408
#define POWER9_PME_PM_L2_RTY_LD 409
#define POWER9_PME_PM_L2_RTY_LD_ALT 410
#define POWER9_PME_PM_L2_RTY_ST 411
#define POWER9_PME_PM_L2_RTY_ST_ALT 412
#define POWER9_PME_PM_L2_SN_M_RD_DONE 413
#define POWER9_PME_PM_L2_SN_M_WR_DONE 414
#define POWER9_PME_PM_L2_SN_M_WR_DONE_ALT 415
#define POWER9_PME_PM_L2_SN_SX_I_DONE 416
#define POWER9_PME_PM_L2_ST_DISP 417
#define POWER9_PME_PM_L2_ST_DISP_ALT 418
#define POWER9_PME_PM_L2_ST_HIT 419
#define POWER9_PME_PM_L2_ST_HIT_ALT 420
#define POWER9_PME_PM_L2_ST_MISS_128B 421
#define POWER9_PME_PM_L2_ST_MISS_64B 422
#define POWER9_PME_PM_L2_ST_MISS 423
#define POWER9_PME_PM_L2_ST 424
#define POWER9_PME_PM_L2_SYS_GUESS_CORRECT 425
#define POWER9_PME_PM_L2_SYS_GUESS_WRONG 426
#define POWER9_PME_PM_L2_SYS_PUMP 427
#define POWER9_PME_PM_L3_CI_HIT 428
#define POWER9_PME_PM_L3_CI_MISS 429
#define POWER9_PME_PM_L3_CINJ 430
#define POWER9_PME_PM_L3_CI_USAGE 431
#define POWER9_PME_PM_L3_CO0_BUSY 432
#define POWER9_PME_PM_L3_CO0_BUSY_ALT 433
#define POWER9_PME_PM_L3_CO_L31 434
#define POWER9_PME_PM_L3_CO_LCO 435
#define POWER9_PME_PM_L3_CO_MEM 436
#define POWER9_PME_PM_L3_CO_MEPF 437
#define POWER9_PME_PM_L3_CO_MEPF_ALT 438
#define POWER9_PME_PM_L3_CO 439
#define POWER9_PME_PM_L3_GRP_GUESS_CORRECT 440
#define POWER9_PME_PM_L3_GRP_GUESS_WRONG_HIGH 441
#define POWER9_PME_PM_L3_GRP_GUESS_WRONG_LOW 442
#define POWER9_PME_PM_L3_HIT 443
#define POWER9_PME_PM_L3_L2_CO_HIT 444
#define POWER9_PME_PM_L3_L2_CO_MISS 445
#define POWER9_PME_PM_L3_LAT_CI_HIT 446
#define POWER9_PME_PM_L3_LAT_CI_MISS 447
#define POWER9_PME_PM_L3_LD_HIT 448
#define POWER9_PME_PM_L3_LD_MISS 449
#define POWER9_PME_PM_L3_LD_PREF 450
#define POWER9_PME_PM_L3_LOC_GUESS_CORRECT 451
#define POWER9_PME_PM_L3_LOC_GUESS_WRONG 452
#define POWER9_PME_PM_L3_MISS 453
#define POWER9_PME_PM_L3_P0_CO_L31 454
#define POWER9_PME_PM_L3_P0_CO_MEM 455
#define POWER9_PME_PM_L3_P0_CO_RTY 456
#define POWER9_PME_PM_L3_P0_CO_RTY_ALT 457
#define POWER9_PME_PM_L3_P0_GRP_PUMP 458
#define POWER9_PME_PM_L3_P0_LCO_DATA 459
#define POWER9_PME_PM_L3_P0_LCO_NO_DATA 460
#define POWER9_PME_PM_L3_P0_LCO_RTY 461
#define POWER9_PME_PM_L3_P0_NODE_PUMP 462
#define POWER9_PME_PM_L3_P0_PF_RTY 463
#define POWER9_PME_PM_L3_P0_PF_RTY_ALT 464
#define POWER9_PME_PM_L3_P0_SYS_PUMP 465
#define POWER9_PME_PM_L3_P1_CO_L31 466
#define POWER9_PME_PM_L3_P1_CO_MEM 467
#define POWER9_PME_PM_L3_P1_CO_RTY 468
#define POWER9_PME_PM_L3_P1_CO_RTY_ALT 469
#define POWER9_PME_PM_L3_P1_GRP_PUMP 470
#define POWER9_PME_PM_L3_P1_LCO_DATA 471
#define POWER9_PME_PM_L3_P1_LCO_NO_DATA 472
#define POWER9_PME_PM_L3_P1_LCO_RTY 473
#define POWER9_PME_PM_L3_P1_NODE_PUMP 474
#define POWER9_PME_PM_L3_P1_PF_RTY 475
#define POWER9_PME_PM_L3_P1_PF_RTY_ALT 476
#define POWER9_PME_PM_L3_P1_SYS_PUMP 477
#define POWER9_PME_PM_L3_P2_LCO_RTY 478
#define POWER9_PME_PM_L3_P3_LCO_RTY 479
#define POWER9_PME_PM_L3_PF0_BUSY 480
#define POWER9_PME_PM_L3_PF0_BUSY_ALT 481
#define POWER9_PME_PM_L3_PF_HIT_L3 482
#define POWER9_PME_PM_L3_PF_MISS_L3 483
#define POWER9_PME_PM_L3_PF_OFF_CHIP_CACHE 484
#define POWER9_PME_PM_L3_PF_OFF_CHIP_MEM 485
#define POWER9_PME_PM_L3_PF_ON_CHIP_CACHE 486
#define POWER9_PME_PM_L3_PF_ON_CHIP_MEM 487
#define POWER9_PME_PM_L3_PF_USAGE 488
#define POWER9_PME_PM_L3_RD0_BUSY 489
#define POWER9_PME_PM_L3_RD0_BUSY_ALT 490
#define POWER9_PME_PM_L3_RD_USAGE 491
#define POWER9_PME_PM_L3_SN0_BUSY 492
#define POWER9_PME_PM_L3_SN0_BUSY_ALT 493
#define POWER9_PME_PM_L3_SN_USAGE 494
#define POWER9_PME_PM_L3_SW_PREF 495
#define POWER9_PME_PM_L3_SYS_GUESS_CORRECT 496
#define POWER9_PME_PM_L3_SYS_GUESS_WRONG 497
#define POWER9_PME_PM_L3_TRANS_PF 498
#define POWER9_PME_PM_L3_WI0_BUSY 499
#define POWER9_PME_PM_L3_WI0_BUSY_ALT 500
#define POWER9_PME_PM_L3_WI_USAGE 501
#define POWER9_PME_PM_LARX_FIN 502
#define POWER9_PME_PM_LD_CMPL 503
#define POWER9_PME_PM_LD_L3MISS_PEND_CYC 504
#define POWER9_PME_PM_LD_MISS_L1_FIN 505
#define POWER9_PME_PM_LD_MISS_L1 506
#define POWER9_PME_PM_LD_REF_L1 507
#define POWER9_PME_PM_LINK_STACK_CORRECT 508
#define POWER9_PME_PM_LINK_STACK_INVALID_PTR 509
#define POWER9_PME_PM_LINK_STACK_WRONG_ADD_PRED 510
#define POWER9_PME_PM_LMQ_EMPTY_CYC 511
#define POWER9_PME_PM_LMQ_MERGE 512
#define POWER9_PME_PM_LRQ_REJECT 513
#define POWER9_PME_PM_LS0_DC_COLLISIONS 514
#define POWER9_PME_PM_LS0_ERAT_MISS_PREF 515
#define POWER9_PME_PM_LS0_LAUNCH_HELD_PREF 516
#define POWER9_PME_PM_LS0_PTE_TABLEWALK_CYC 517
#define POWER9_PME_PM_LS0_TM_DISALLOW 518
#define POWER9_PME_PM_LS0_UNALIGNED_LD 519
#define POWER9_PME_PM_LS0_UNALIGNED_ST 520
#define POWER9_PME_PM_LS1_DC_COLLISIONS 521
#define POWER9_PME_PM_LS1_ERAT_MISS_PREF 522
#define POWER9_PME_PM_LS1_LAUNCH_HELD_PREF 523
#define POWER9_PME_PM_LS1_PTE_TABLEWALK_CYC 524
#define POWER9_PME_PM_LS1_TM_DISALLOW 525
#define POWER9_PME_PM_LS1_UNALIGNED_LD 526
#define POWER9_PME_PM_LS1_UNALIGNED_ST 527
#define POWER9_PME_PM_LS2_DC_COLLISIONS 528
#define POWER9_PME_PM_LS2_ERAT_MISS_PREF 529
#define POWER9_PME_PM_LS2_TM_DISALLOW 530
#define POWER9_PME_PM_LS2_UNALIGNED_LD 531
#define POWER9_PME_PM_LS2_UNALIGNED_ST 532
#define POWER9_PME_PM_LS3_DC_COLLISIONS 533
#define POWER9_PME_PM_LS3_ERAT_MISS_PREF 534
#define POWER9_PME_PM_LS3_TM_DISALLOW 535
#define POWER9_PME_PM_LS3_UNALIGNED_LD 536
#define POWER9_PME_PM_LS3_UNALIGNED_ST 537
#define POWER9_PME_PM_LSU0_1_LRQF_FULL_CYC 538
#define POWER9_PME_PM_LSU0_ERAT_HIT 539
#define POWER9_PME_PM_LSU0_FALSE_LHS 540
#define POWER9_PME_PM_LSU0_L1_CAM_CANCEL 541
#define POWER9_PME_PM_LSU0_LDMX_FIN 542
#define POWER9_PME_PM_LSU0_LMQ_S0_VALID 543
#define POWER9_PME_PM_LSU0_LRQ_S0_VALID_CYC 544
#define POWER9_PME_PM_LSU0_SET_MPRED 545
#define POWER9_PME_PM_LSU0_SRQ_S0_VALID_CYC 546
#define POWER9_PME_PM_LSU0_STORE_REJECT 547
#define POWER9_PME_PM_LSU0_TM_L1_HIT 548
#define POWER9_PME_PM_LSU0_TM_L1_MISS 549
#define POWER9_PME_PM_LSU1_ERAT_HIT 550
#define POWER9_PME_PM_LSU1_FALSE_LHS 551
#define POWER9_PME_PM_LSU1_L1_CAM_CANCEL 552
#define POWER9_PME_PM_LSU1_LDMX_FIN 553
#define POWER9_PME_PM_LSU1_SET_MPRED 554
#define POWER9_PME_PM_LSU1_STORE_REJECT 555
#define POWER9_PME_PM_LSU1_TM_L1_HIT 556
#define POWER9_PME_PM_LSU1_TM_L1_MISS 557
#define POWER9_PME_PM_LSU2_3_LRQF_FULL_CYC 558
#define POWER9_PME_PM_LSU2_ERAT_HIT 559
#define POWER9_PME_PM_LSU2_FALSE_LHS 560
#define POWER9_PME_PM_LSU2_L1_CAM_CANCEL 561
#define POWER9_PME_PM_LSU2_LDMX_FIN 562
#define POWER9_PME_PM_LSU2_SET_MPRED 563
#define POWER9_PME_PM_LSU2_STORE_REJECT 564
#define POWER9_PME_PM_LSU2_TM_L1_HIT 565
#define POWER9_PME_PM_LSU2_TM_L1_MISS 566
#define POWER9_PME_PM_LSU3_ERAT_HIT 567
#define POWER9_PME_PM_LSU3_FALSE_LHS 568
#define POWER9_PME_PM_LSU3_L1_CAM_CANCEL 569
#define POWER9_PME_PM_LSU3_LDMX_FIN 570
#define POWER9_PME_PM_LSU3_SET_MPRED 571
#define POWER9_PME_PM_LSU3_STORE_REJECT 572
#define POWER9_PME_PM_LSU3_TM_L1_HIT 573
#define POWER9_PME_PM_LSU3_TM_L1_MISS 574
#define POWER9_PME_PM_LSU_DERAT_MISS 575
#define POWER9_PME_PM_LSU_FIN 576
#define POWER9_PME_PM_LSU_FLUSH_ATOMIC 577
#define POWER9_PME_PM_LSU_FLUSH_CI 578
#define POWER9_PME_PM_LSU_FLUSH_EMSH 579
#define POWER9_PME_PM_LSU_FLUSH_LARX_STCX 580
#define POWER9_PME_PM_LSU_FLUSH_LHL_SHL 581
#define POWER9_PME_PM_LSU_FLUSH_LHS 582
#define POWER9_PME_PM_LSU_FLUSH_NEXT 583
#define POWER9_PME_PM_LSU_FLUSH_OTHER 584
#define POWER9_PME_PM_LSU_FLUSH_RELAUNCH_MISS 585
#define POWER9_PME_PM_LSU_FLUSH_SAO 586
#define POWER9_PME_PM_LSU_FLUSH_UE 587
#define POWER9_PME_PM_LSU_FLUSH_WRK_ARND 588
#define POWER9_PME_PM_LSU_LMQ_FULL_CYC 589
#define POWER9_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC 590
#define POWER9_PME_PM_LSU_NCST 591
#define POWER9_PME_PM_LSU_REJECT_ERAT_MISS 592
#define POWER9_PME_PM_LSU_REJECT_LHS 593
#define POWER9_PME_PM_LSU_REJECT_LMQ_FULL 594
#define POWER9_PME_PM_LSU_SRQ_FULL_CYC 595
#define POWER9_PME_PM_LSU_STCX_FAIL 596
#define POWER9_PME_PM_LSU_STCX 597
#define POWER9_PME_PM_LWSYNC 598
#define POWER9_PME_PM_MATH_FLOP_CMPL 599
#define POWER9_PME_PM_MEM_CO 600
#define POWER9_PME_PM_MEM_LOC_THRESH_IFU 601
#define POWER9_PME_PM_MEM_LOC_THRESH_LSU_HIGH 602
#define POWER9_PME_PM_MEM_LOC_THRESH_LSU_MED 603
#define POWER9_PME_PM_MEM_PREF 604
#define POWER9_PME_PM_MEM_READ 605
#define POWER9_PME_PM_MEM_RWITM 606
#define POWER9_PME_PM_MRK_BACK_BR_CMPL 607
#define POWER9_PME_PM_MRK_BR_2PATH 608
#define POWER9_PME_PM_MRK_BR_CMPL 609
#define POWER9_PME_PM_MRK_BR_MPRED_CMPL 610
#define POWER9_PME_PM_MRK_BR_TAKEN_CMPL 611
#define POWER9_PME_PM_MRK_BRU_FIN 612
#define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC 613
#define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD 614
#define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC 615
#define POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR 616
#define POWER9_PME_PM_MRK_DATA_FROM_DL4_CYC 617
#define POWER9_PME_PM_MRK_DATA_FROM_DL4 618
#define POWER9_PME_PM_MRK_DATA_FROM_DMEM_CYC 619
#define POWER9_PME_PM_MRK_DATA_FROM_DMEM 620
#define POWER9_PME_PM_MRK_DATA_FROM_L21_MOD_CYC 621
#define POWER9_PME_PM_MRK_DATA_FROM_L21_MOD 622
#define POWER9_PME_PM_MRK_DATA_FROM_L21_SHR_CYC 623
#define POWER9_PME_PM_MRK_DATA_FROM_L21_SHR 624
#define POWER9_PME_PM_MRK_DATA_FROM_L2_CYC 625
#define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC 626
#define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST 627
#define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC 628
#define POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER 629
#define POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC 630
#define POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF 631
#define POWER9_PME_PM_MRK_DATA_FROM_L2MISS_CYC 632
#define POWER9_PME_PM_MRK_DATA_FROM_L2MISS 633
#define POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC 634
#define POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT 635
#define POWER9_PME_PM_MRK_DATA_FROM_L2 636
#define POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_MOD_CYC 637
#define POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_MOD 638
#define POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_SHR_CYC 639
#define POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_SHR 640
#define POWER9_PME_PM_MRK_DATA_FROM_L31_MOD_CYC 641
#define POWER9_PME_PM_MRK_DATA_FROM_L31_MOD 642
#define POWER9_PME_PM_MRK_DATA_FROM_L31_SHR_CYC 643
#define POWER9_PME_PM_MRK_DATA_FROM_L31_SHR 644
#define POWER9_PME_PM_MRK_DATA_FROM_L3_CYC 645
#define POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC 646
#define POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT 647
#define POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC 648
#define POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF 649
#define POWER9_PME_PM_MRK_DATA_FROM_L3MISS_CYC 650
#define POWER9_PME_PM_MRK_DATA_FROM_L3MISS 651
#define POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC 652
#define POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT 653
#define POWER9_PME_PM_MRK_DATA_FROM_L3 654
#define POWER9_PME_PM_MRK_DATA_FROM_LL4_CYC 655
#define POWER9_PME_PM_MRK_DATA_FROM_LL4 656
#define POWER9_PME_PM_MRK_DATA_FROM_LMEM_CYC 657
#define POWER9_PME_PM_MRK_DATA_FROM_LMEM 658
#define POWER9_PME_PM_MRK_DATA_FROM_MEMORY_CYC 659
#define POWER9_PME_PM_MRK_DATA_FROM_MEMORY 660
#define POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC 661
#define POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE 662
#define POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC 663
#define POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE 664
#define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC 665
#define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD 666
#define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC 667
#define POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR 668
#define POWER9_PME_PM_MRK_DATA_FROM_RL4_CYC 669
#define POWER9_PME_PM_MRK_DATA_FROM_RL4 670
#define POWER9_PME_PM_MRK_DATA_FROM_RMEM_CYC 671
#define POWER9_PME_PM_MRK_DATA_FROM_RMEM 672
#define POWER9_PME_PM_MRK_DCACHE_RELOAD_INTV 673
#define POWER9_PME_PM_MRK_DERAT_MISS_16G 674
#define POWER9_PME_PM_MRK_DERAT_MISS_16M 675
#define POWER9_PME_PM_MRK_DERAT_MISS_1G 676
#define POWER9_PME_PM_MRK_DERAT_MISS_2M 677
#define POWER9_PME_PM_MRK_DERAT_MISS_4K 678
#define POWER9_PME_PM_MRK_DERAT_MISS_64K 679
#define POWER9_PME_PM_MRK_DERAT_MISS 680
#define POWER9_PME_PM_MRK_DFU_FIN 681
#define POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD 682
#define POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR 683
#define POWER9_PME_PM_MRK_DPTEG_FROM_DL4 684
#define POWER9_PME_PM_MRK_DPTEG_FROM_DMEM 685
#define POWER9_PME_PM_MRK_DPTEG_FROM_L21_MOD 686
#define POWER9_PME_PM_MRK_DPTEG_FROM_L21_SHR 687
#define POWER9_PME_PM_MRK_DPTEG_FROM_L2_MEPF 688
#define POWER9_PME_PM_MRK_DPTEG_FROM_L2MISS 689
#define POWER9_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT 690
#define POWER9_PME_PM_MRK_DPTEG_FROM_L2 691
#define POWER9_PME_PM_MRK_DPTEG_FROM_L31_ECO_MOD 692
#define POWER9_PME_PM_MRK_DPTEG_FROM_L31_ECO_SHR 693
#define POWER9_PME_PM_MRK_DPTEG_FROM_L31_MOD 694
#define POWER9_PME_PM_MRK_DPTEG_FROM_L31_SHR 695
#define POWER9_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT 696
#define POWER9_PME_PM_MRK_DPTEG_FROM_L3_MEPF 697
#define POWER9_PME_PM_MRK_DPTEG_FROM_L3MISS 698
#define POWER9_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT 699
#define POWER9_PME_PM_MRK_DPTEG_FROM_L3 700
#define POWER9_PME_PM_MRK_DPTEG_FROM_LL4 701
#define POWER9_PME_PM_MRK_DPTEG_FROM_LMEM 702
#define POWER9_PME_PM_MRK_DPTEG_FROM_MEMORY 703
#define POWER9_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE 704
#define POWER9_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE 705
#define POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD 706
#define POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR 707
#define POWER9_PME_PM_MRK_DPTEG_FROM_RL4 708
#define POWER9_PME_PM_MRK_DPTEG_FROM_RMEM 709
#define POWER9_PME_PM_MRK_DTLB_MISS_16G 710
#define POWER9_PME_PM_MRK_DTLB_MISS_16M 711
#define POWER9_PME_PM_MRK_DTLB_MISS_1G 712
#define POWER9_PME_PM_MRK_DTLB_MISS_4K 713
#define POWER9_PME_PM_MRK_DTLB_MISS_64K 714
#define POWER9_PME_PM_MRK_DTLB_MISS 715
#define POWER9_PME_PM_MRK_FAB_RSP_BKILL_CYC 716
#define POWER9_PME_PM_MRK_FAB_RSP_BKILL 717
#define POWER9_PME_PM_MRK_FAB_RSP_CLAIM_RTY 718
#define POWER9_PME_PM_MRK_FAB_RSP_DCLAIM_CYC 719
#define POWER9_PME_PM_MRK_FAB_RSP_DCLAIM 720
#define POWER9_PME_PM_MRK_FAB_RSP_RD_RTY 721
#define POWER9_PME_PM_MRK_FAB_RSP_RD_T_INTV 722
#define POWER9_PME_PM_MRK_FAB_RSP_RWITM_CYC 723
#define POWER9_PME_PM_MRK_FAB_RSP_RWITM_RTY 724
#define POWER9_PME_PM_MRK_FXU_FIN 725
#define POWER9_PME_PM_MRK_IC_MISS 726
#define POWER9_PME_PM_MRK_INST_CMPL 727
#define POWER9_PME_PM_MRK_INST_DECODED 728
#define POWER9_PME_PM_MRK_INST_DISP 729
#define POWER9_PME_PM_MRK_INST_FIN 730
#define POWER9_PME_PM_MRK_INST_FROM_L3MISS 731
#define POWER9_PME_PM_MRK_INST_ISSUED 732
#define POWER9_PME_PM_MRK_INST_TIMEO 733
#define POWER9_PME_PM_MRK_INST 734
#define POWER9_PME_PM_MRK_L1_ICACHE_MISS 735
#define POWER9_PME_PM_MRK_L1_RELOAD_VALID 736
#define POWER9_PME_PM_MRK_L2_RC_DISP 737
#define POWER9_PME_PM_MRK_L2_RC_DONE 738
#define POWER9_PME_PM_MRK_L2_TM_REQ_ABORT 739
#define POWER9_PME_PM_MRK_L2_TM_ST_ABORT_SISTER 740
#define POWER9_PME_PM_MRK_LARX_FIN 741
#define POWER9_PME_PM_MRK_LD_MISS_EXPOSED_CYC 742
#define POWER9_PME_PM_MRK_LD_MISS_L1_CYC 743
#define POWER9_PME_PM_MRK_LD_MISS_L1 744
#define POWER9_PME_PM_MRK_LSU_DERAT_MISS 745
#define POWER9_PME_PM_MRK_LSU_FIN 746
#define POWER9_PME_PM_MRK_LSU_FLUSH_ATOMIC 747
#define POWER9_PME_PM_MRK_LSU_FLUSH_EMSH 748
#define POWER9_PME_PM_MRK_LSU_FLUSH_LARX_STCX 749
#define POWER9_PME_PM_MRK_LSU_FLUSH_LHL_SHL 750
#define POWER9_PME_PM_MRK_LSU_FLUSH_LHS 751
#define POWER9_PME_PM_MRK_LSU_FLUSH_RELAUNCH_MISS 752
#define POWER9_PME_PM_MRK_LSU_FLUSH_SAO 753
#define POWER9_PME_PM_MRK_LSU_FLUSH_UE 754
#define POWER9_PME_PM_MRK_NTC_CYC 755
#define POWER9_PME_PM_MRK_NTF_FIN 756
#define POWER9_PME_PM_MRK_PROBE_NOP_CMPL 757
#define POWER9_PME_PM_MRK_RUN_CYC 758
#define POWER9_PME_PM_MRK_STALL_CMPLU_CYC 759
#define POWER9_PME_PM_MRK_ST_CMPL_INT 760
#define POWER9_PME_PM_MRK_ST_CMPL 761
#define POWER9_PME_PM_MRK_STCX_FAIL 762
#define POWER9_PME_PM_MRK_STCX_FIN 763
#define POWER9_PME_PM_MRK_ST_DONE_L2 764
#define POWER9_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC 765
#define POWER9_PME_PM_MRK_ST_FWD 766
#define POWER9_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC 767
#define POWER9_PME_PM_MRK_ST_NEST 768
#define POWER9_PME_PM_MRK_TEND_FAIL 769
#define POWER9_PME_PM_MRK_VSU_FIN 770
#define POWER9_PME_PM_MULT_MRK 771
#define POWER9_PME_PM_NEST_REF_CLK 772
#define POWER9_PME_PM_NON_DATA_STORE 773
#define POWER9_PME_PM_NON_FMA_FLOP_CMPL 774
#define POWER9_PME_PM_NON_MATH_FLOP_CMPL 775
#define POWER9_PME_PM_NON_TM_RST_SC 776
#define POWER9_PME_PM_NTC_ALL_FIN 777
#define POWER9_PME_PM_NTC_FIN 778
#define POWER9_PME_PM_NTC_ISSUE_HELD_ARB 779
#define POWER9_PME_PM_NTC_ISSUE_HELD_DARQ_FULL 780
#define POWER9_PME_PM_NTC_ISSUE_HELD_OTHER 781
#define POWER9_PME_PM_PARTIAL_ST_FIN 782
#define POWER9_PME_PM_PMC1_OVERFLOW 783
#define POWER9_PME_PM_PMC1_REWIND 784
#define POWER9_PME_PM_PMC1_SAVED 785
#define POWER9_PME_PM_PMC2_OVERFLOW 786
#define POWER9_PME_PM_PMC2_REWIND 787
#define POWER9_PME_PM_PMC2_SAVED 788
#define POWER9_PME_PM_PMC3_OVERFLOW 789
#define POWER9_PME_PM_PMC3_REWIND 790
#define POWER9_PME_PM_PMC3_SAVED 791
#define POWER9_PME_PM_PMC4_OVERFLOW 792
#define POWER9_PME_PM_PMC4_REWIND 793
#define POWER9_PME_PM_PMC4_SAVED 794
#define POWER9_PME_PM_PMC5_OVERFLOW 795
#define POWER9_PME_PM_PMC6_OVERFLOW 796
#define POWER9_PME_PM_PROBE_NOP_DISP 797
#define POWER9_PME_PM_PTE_PREFETCH 798
#define POWER9_PME_PM_PTESYNC 799
#define POWER9_PME_PM_PUMP_CPRED 800
#define POWER9_PME_PM_PUMP_MPRED 801
#define POWER9_PME_PM_RADIX_PWC_L1_HIT 802
#define POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L2 803
#define POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3MISS 804
#define POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3 805
#define POWER9_PME_PM_RADIX_PWC_L2_HIT 806
#define POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L2 807
#define POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L3 808
#define POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L2 809
#define POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3MISS 810
#define POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3 811
#define POWER9_PME_PM_RADIX_PWC_L3_HIT 812
#define POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L2 813
#define POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L3 814
#define POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L2 815
#define POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3MISS 816
#define POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3 817
#define POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L2 818
#define POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3MISS 819
#define POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3 820
#define POWER9_PME_PM_RADIX_PWC_MISS 821
#define POWER9_PME_PM_RC0_BUSY 822
#define POWER9_PME_PM_RC0_BUSY_ALT 823
#define POWER9_PME_PM_RC_USAGE 824
#define POWER9_PME_PM_RD_CLEARING_SC 825
#define POWER9_PME_PM_RD_FORMING_SC 826
#define POWER9_PME_PM_RD_HIT_PF 827
#define POWER9_PME_PM_RUN_CYC_SMT2_MODE 828
#define POWER9_PME_PM_RUN_CYC_SMT4_MODE 829
#define POWER9_PME_PM_RUN_CYC_ST_MODE 830
#define POWER9_PME_PM_RUN_CYC 831
#define POWER9_PME_PM_RUN_INST_CMPL 832
#define POWER9_PME_PM_RUN_PURR 833
#define POWER9_PME_PM_RUN_SPURR 834
#define POWER9_PME_PM_S2Q_FULL 835
#define POWER9_PME_PM_SCALAR_FLOP_CMPL 836
#define POWER9_PME_PM_SHL_CREATED 837
#define POWER9_PME_PM_SHL_ST_DEP_CREATED 838
#define POWER9_PME_PM_SHL_ST_DISABLE 839
#define POWER9_PME_PM_SLB_TABLEWALK_CYC 840
#define POWER9_PME_PM_SN0_BUSY 841
#define POWER9_PME_PM_SN0_BUSY_ALT 842
#define POWER9_PME_PM_SN_HIT 843
#define POWER9_PME_PM_SN_INVL 844
#define POWER9_PME_PM_SN_MISS 845
#define POWER9_PME_PM_SNOOP_TLBIE 846
#define POWER9_PME_PM_SNP_TM_HIT_M 847
#define POWER9_PME_PM_SNP_TM_HIT_T 848
#define POWER9_PME_PM_SN_USAGE 849
#define POWER9_PME_PM_SP_FLOP_CMPL 850
#define POWER9_PME_PM_SRQ_EMPTY_CYC 851
#define POWER9_PME_PM_SRQ_SYNC_CYC 852
#define POWER9_PME_PM_STALL_END_ICT_EMPTY 853
#define POWER9_PME_PM_ST_CAUSED_FAIL 854
#define POWER9_PME_PM_ST_CMPL 855
#define POWER9_PME_PM_STCX_FAIL 856
#define POWER9_PME_PM_STCX_FIN 857
#define POWER9_PME_PM_STCX_SUCCESS_CMPL 858
#define POWER9_PME_PM_ST_FIN 859
#define POWER9_PME_PM_ST_FWD 860
#define POWER9_PME_PM_ST_MISS_L1 861
#define POWER9_PME_PM_STOP_FETCH_PENDING_CYC 862
#define POWER9_PME_PM_SUSPENDED 863
#define POWER9_PME_PM_SYNC_MRK_BR_LINK 864
#define POWER9_PME_PM_SYNC_MRK_BR_MPRED 865
#define POWER9_PME_PM_SYNC_MRK_FX_DIVIDE 866
#define POWER9_PME_PM_SYNC_MRK_L2HIT 867
#define POWER9_PME_PM_SYNC_MRK_L2MISS 868
#define POWER9_PME_PM_SYNC_MRK_L3MISS 869
#define POWER9_PME_PM_SYNC_MRK_PROBE_NOP 870
#define POWER9_PME_PM_SYS_PUMP_CPRED 871
#define POWER9_PME_PM_SYS_PUMP_MPRED_RTY 872
#define POWER9_PME_PM_SYS_PUMP_MPRED 873
#define POWER9_PME_PM_TABLEWALK_CYC_PREF 874
#define POWER9_PME_PM_TABLEWALK_CYC 875
#define POWER9_PME_PM_TAGE_CORRECT_TAKEN_CMPL 876
#define POWER9_PME_PM_TAGE_CORRECT 877
#define POWER9_PME_PM_TAGE_OVERRIDE_WRONG_SPEC 878
#define POWER9_PME_PM_TAGE_OVERRIDE_WRONG 879
#define POWER9_PME_PM_TAKEN_BR_MPRED_CMPL 880
#define POWER9_PME_PM_TB_BIT_TRANS 881
#define POWER9_PME_PM_TEND_PEND_CYC 882
#define POWER9_PME_PM_THRD_ALL_RUN_CYC 883
#define POWER9_PME_PM_THRD_CONC_RUN_INST 884
#define POWER9_PME_PM_THRD_PRIO_0_1_CYC 885
#define POWER9_PME_PM_THRD_PRIO_2_3_CYC 886
#define POWER9_PME_PM_THRD_PRIO_4_5_CYC 887
#define POWER9_PME_PM_THRD_PRIO_6_7_CYC 888
#define POWER9_PME_PM_THRESH_ACC 889
#define POWER9_PME_PM_THRESH_EXC_1024 890
#define POWER9_PME_PM_THRESH_EXC_128 891
#define POWER9_PME_PM_THRESH_EXC_2048 892
#define POWER9_PME_PM_THRESH_EXC_256 893
#define POWER9_PME_PM_THRESH_EXC_32 894
#define POWER9_PME_PM_THRESH_EXC_4096 895
#define POWER9_PME_PM_THRESH_EXC_512 896
#define POWER9_PME_PM_THRESH_EXC_64 897
#define POWER9_PME_PM_THRESH_MET 898
#define POWER9_PME_PM_THRESH_NOT_MET 899
#define POWER9_PME_PM_TLB_HIT 900
#define POWER9_PME_PM_TLBIE_FIN 901
#define POWER9_PME_PM_TLB_MISS 902
#define POWER9_PME_PM_TM_ABORTS 903
#define POWER9_PME_PM_TMA_REQ_L2 904
#define POWER9_PME_PM_TM_CAM_OVERFLOW 905
#define POWER9_PME_PM_TM_CAP_OVERFLOW 906
#define POWER9_PME_PM_TM_FAIL_CONF_NON_TM 907
#define POWER9_PME_PM_TM_FAIL_CONF_TM 908
#define POWER9_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW 909
#define POWER9_PME_PM_TM_FAIL_NON_TX_CONFLICT 910
#define POWER9_PME_PM_TM_FAIL_SELF 911
#define POWER9_PME_PM_TM_FAIL_TLBIE 912
#define POWER9_PME_PM_TM_FAIL_TX_CONFLICT 913
#define POWER9_PME_PM_TM_FAV_CAUSED_FAIL 914
#define POWER9_PME_PM_TM_FAV_TBEGIN 915
#define POWER9_PME_PM_TM_LD_CAUSED_FAIL 916
#define POWER9_PME_PM_TM_LD_CONF 917
#define POWER9_PME_PM_TM_NESTED_TBEGIN 918
#define POWER9_PME_PM_TM_NESTED_TEND 919
#define POWER9_PME_PM_TM_NON_FAV_TBEGIN 920
#define POWER9_PME_PM_TM_OUTER_TBEGIN_DISP 921
#define POWER9_PME_PM_TM_OUTER_TBEGIN 922
#define POWER9_PME_PM_TM_OUTER_TEND 923
#define POWER9_PME_PM_TM_PASSED 924
#define POWER9_PME_PM_TM_RST_SC 925
#define POWER9_PME_PM_TM_SC_CO 926
#define POWER9_PME_PM_TM_ST_CAUSED_FAIL 927
#define POWER9_PME_PM_TM_ST_CONF 928
#define POWER9_PME_PM_TM_TABORT_TRECLAIM 929
#define POWER9_PME_PM_TM_TRANS_RUN_CYC 930
#define POWER9_PME_PM_TM_TRANS_RUN_INST 931
#define POWER9_PME_PM_TM_TRESUME 932
#define POWER9_PME_PM_TM_TSUSPEND 933
#define POWER9_PME_PM_TM_TX_PASS_RUN_CYC 934
#define POWER9_PME_PM_TM_TX_PASS_RUN_INST 935
#define POWER9_PME_PM_VECTOR_FLOP_CMPL 936
#define POWER9_PME_PM_VECTOR_LD_CMPL 937
#define POWER9_PME_PM_VECTOR_ST_CMPL 938
#define POWER9_PME_PM_VSU_DP_FSQRT_FDIV 939
#define POWER9_PME_PM_VSU_FIN 940
#define POWER9_PME_PM_VSU_FSQRT_FDIV 941
#define POWER9_PME_PM_VSU_NON_FLOP_CMPL 942
#define POWER9_PME_PM_XLATE_HPT_MODE 943
#define POWER9_PME_PM_XLATE_MISS 944
#define POWER9_PME_PM_XLATE_RADIX_MODE 945
#define POWER9_PME_PM_BR_2PATH_ALT 946
#define POWER9_PME_PM_CYC_ALT 947
#define POWER9_PME_PM_CYC_ALT2 948
#define POWER9_PME_PM_CYC_ALT3 949
#define POWER9_PME_PM_INST_CMPL_ALT 950
#define POWER9_PME_PM_INST_CMPL_ALT2 951
#define POWER9_PME_PM_INST_CMPL_ALT3 952
#define POWER9_PME_PM_INST_DISP_ALT 953
#define POWER9_PME_PM_LD_MISS_L1_ALT 954
#define POWER9_PME_PM_SUSPENDED_ALT 955
#define POWER9_PME_PM_SUSPENDED_ALT2 956
#define POWER9_PME_PM_SUSPENDED_ALT3 957

static const pme_power_entry_t power9_pe[] = {
[ POWER9_PME_PM_1FLOP_CMPL ] = {
	.pme_name = "PM_1FLOP_CMPL",
	.pme_code = 0x0000045050,
	.pme_short_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed",
	.pme_long_desc = "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed",
},
[ POWER9_PME_PM_1PLUS_PPC_CMPL ] = {
	.pme_name = "PM_1PLUS_PPC_CMPL",
	.pme_code = 0x00000100F2,
	.pme_short_desc = "1 or more ppc insts finished",
	.pme_long_desc = "1 or more ppc insts finished",
},
[ POWER9_PME_PM_1PLUS_PPC_DISP ] = {
	.pme_name = "PM_1PLUS_PPC_DISP",
	.pme_code = 0x00000400F2,
	.pme_short_desc = "Cycles at least one Instr Dispatched",
	.pme_long_desc = "Cycles at least one Instr Dispatched",
},
[ POWER9_PME_PM_2FLOP_CMPL ] = {
	.pme_name = "PM_2FLOP_CMPL",
	.pme_code = 0x000004D052,
	.pme_short_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ",
	.pme_long_desc = "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ",
},
[ POWER9_PME_PM_4FLOP_CMPL ] = {
	.pme_name = "PM_4FLOP_CMPL",
	.pme_code = 0x0000045052,
	.pme_short_desc = "4 FLOP instruction completed",
	.pme_long_desc = "4 FLOP instruction completed",
},
[ POWER9_PME_PM_8FLOP_CMPL ] = {
	.pme_name = "PM_8FLOP_CMPL",
	.pme_code = 0x000004D054,
	.pme_short_desc = "8 FLOP instruction completed",
	.pme_long_desc = "8 FLOP instruction completed",
},
[ POWER9_PME_PM_ANY_THRD_RUN_CYC ] = {
	.pme_name = "PM_ANY_THRD_RUN_CYC",
	.pme_code = 0x00000100FA,
	.pme_short_desc = "Cycles in which at least one thread has the run latch set",
	.pme_long_desc = "Cycles in which at least one thread has the run latch set",
},
[ POWER9_PME_PM_BACK_BR_CMPL ] = {
	.pme_name = "PM_BACK_BR_CMPL",
	.pme_code = 0x000002505E,
	.pme_short_desc = "Branch instruction completed with a target address less than current instruction address",
	.pme_long_desc = "Branch instruction completed with a target address less than current instruction address",
},
[ POWER9_PME_PM_BANK_CONFLICT ] = {
	.pme_name = "PM_BANK_CONFLICT",
	.pme_code = 0x0000004880,
	.pme_short_desc = "Read blocked due to interleave conflict.",
	.pme_long_desc = "Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle.",
},
[ POWER9_PME_PM_BFU_BUSY ] = {
	.pme_name = "PM_BFU_BUSY",
	.pme_code = 0x000003005C,
	.pme_short_desc = "Cycles in which all 4 Binary Floating Point units are busy.",
	.pme_long_desc = "Cycles in which all 4 Binary Floating Point units are busy. The BFU is running at capacity",
},
/* See also alternate entries for 0000020036 / POWER9_PME_PM_BR_2PATH with code(s) 0000040036 at the bottom of this table. \n */
[ POWER9_PME_PM_BR_2PATH ] = {
	.pme_name = "PM_BR_2PATH",
	.pme_code = 0x0000020036,
	.pme_short_desc = "Branches that are not strongly biased",
	.pme_long_desc = "Branches that are not strongly biased",
},
[ POWER9_PME_PM_BR_CMPL ] = {
	.pme_name = "PM_BR_CMPL",
	.pme_code = 0x000004D05E,
	.pme_short_desc = "Any Branch instruction completed",
	.pme_long_desc = "Any Branch instruction completed",
},
[ POWER9_PME_PM_BR_CORECT_PRED_TAKEN_CMPL ] = {
	.pme_name = "PM_BR_CORECT_PRED_TAKEN_CMPL",
	.pme_code = 0x000000489C,
	.pme_short_desc = "Conditional Branch Completed in which the HW correctly predicted the direction as taken.",
	.pme_long_desc = "Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time",
},
[ POWER9_PME_PM_BR_MPRED_CCACHE ] = {
	.pme_name = "PM_BR_MPRED_CCACHE",
	.pme_code = 0x00000040AC,
	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction",
	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction",
},
[ POWER9_PME_PM_BR_MPRED_CMPL ] = {
	.pme_name = "PM_BR_MPRED_CMPL",
	.pme_code = 0x00000400F6,
	.pme_short_desc = "Number of Branch Mispredicts",
	.pme_long_desc = "Number of Branch Mispredicts",
},
[ POWER9_PME_PM_BR_MPRED_LSTACK ] = {
	.pme_name = "PM_BR_MPRED_LSTACK",
	.pme_code = 0x00000048AC,
	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction",
	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction",
},
[ POWER9_PME_PM_BR_MPRED_PCACHE ] = {
	.pme_name = "PM_BR_MPRED_PCACHE",
	.pme_code = 0x00000048B0,
	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to pattern cache prediction",
	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to pattern cache prediction",
},
[ POWER9_PME_PM_BR_MPRED_TAKEN_CR ] = {
	.pme_name = "PM_BR_MPRED_TAKEN_CR",
	.pme_code = 0x00000040B8,
	.pme_short_desc = "A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction).",
	.pme_long_desc = "A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Direction Prediction).",
},
[ POWER9_PME_PM_BR_MPRED_TAKEN_TA ] = {
	.pme_name = "PM_BR_MPRED_TAKEN_TA",
	.pme_code = 0x00000048B8,
	.pme_short_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack.",
	.pme_long_desc = "Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event.",
},
[ POWER9_PME_PM_BR_PRED_CCACHE ] = {
	.pme_name = "PM_BR_PRED_CCACHE",
	.pme_code = 0x00000040A4,
	.pme_short_desc = "Conditional Branch Completed that used the Count Cache for Target Prediction",
	.pme_long_desc = "Conditional Branch Completed that used the Count Cache for Target Prediction",
},
[ POWER9_PME_PM_BR_PRED_LSTACK ] = {
	.pme_name = "PM_BR_PRED_LSTACK",
	.pme_code = 0x00000040A8,
	.pme_short_desc = "Conditional Branch Completed that used the Link Stack for Target Prediction",
	.pme_long_desc = "Conditional Branch Completed that used the Link Stack for Target Prediction",
},
[ POWER9_PME_PM_BR_PRED_PCACHE ] = {
	.pme_name = "PM_BR_PRED_PCACHE",
	.pme_code = 0x00000048A0,
	.pme_short_desc = "Conditional branch completed that used pattern cache prediction",
	.pme_long_desc = "Conditional branch completed that used pattern cache prediction",
},
[ POWER9_PME_PM_BR_PRED_TAKEN_CR ] = {
	.pme_name = "PM_BR_PRED_TAKEN_CR",
	.pme_code = 0x00000040B0,
	.pme_short_desc = "Conditional Branch that had its direction predicted.",
	.pme_long_desc = "Conditional Branch that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and branches",
},
[ POWER9_PME_PM_BR_PRED_TA ] = {
	.pme_name = "PM_BR_PRED_TA",
	.pme_code = 0x00000040B4,
	.pme_short_desc = "Conditional Branch Completed that had its target address predicted.",
	.pme_long_desc = "Conditional Branch Completed that had its target address predicted. Only XL-form branches set this event. This equal the sum of CCACHE, LSTACK, and PCACHE",
},
[ POWER9_PME_PM_BR_PRED ] = {
	.pme_name = "PM_BR_PRED",
	.pme_code = 0x000000409C,
	.pme_short_desc = "Conditional Branch Executed in which the HW predicted the Direction or Target.",
	.pme_long_desc = "Conditional Branch Executed in which the HW predicted the Direction or Target. Includes taken and not taken and is counted at execution time",
},
[ POWER9_PME_PM_BR_TAKEN_CMPL ] = {
	.pme_name = "PM_BR_TAKEN_CMPL",
	.pme_code = 0x00000200FA,
	.pme_short_desc = "New event for Branch Taken",
	.pme_long_desc = "New event for Branch Taken",
},
[ POWER9_PME_PM_BRU_FIN ] = {
	.pme_name = "PM_BRU_FIN",
	.pme_code = 0x0000010068,
	.pme_short_desc = "Branch Instruction Finished",
	.pme_long_desc = "Branch Instruction Finished",
},
[ POWER9_PME_PM_BR_UNCOND ] = {
	.pme_name = "PM_BR_UNCOND",
	.pme_code = 0x00000040A0,
	.pme_short_desc = "Unconditional Branch Completed.",
	.pme_long_desc = "Unconditional Branch Completed. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was covenrted to a Resolve.",
},
[ POWER9_PME_PM_BTAC_BAD_RESULT ] = {
	.pme_name = "PM_BTAC_BAD_RESULT",
	.pme_code = 0x00000050B0,
	.pme_short_desc = "BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common).",
	.pme_long_desc = "BTAC thinks branch will be taken but it is either predicted not-taken by the BHT, or the target address is wrong (less common). In both cases, a redirect will happen",
},
[ POWER9_PME_PM_BTAC_GOOD_RESULT ] = {
	.pme_name = "PM_BTAC_GOOD_RESULT",
	.pme_code = 0x00000058B0,
	.pme_short_desc = "BTAC predicts a taken branch and the BHT agrees, and the target address is correct",
	.pme_long_desc = "BTAC predicts a taken branch and the BHT agrees, and the target address is correct",
},
[ POWER9_PME_PM_CHIP_PUMP_CPRED ] = {
	.pme_name = "PM_CHIP_PUMP_CPRED",
	.pme_code = 0x0000010050,
	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER9_PME_PM_CLB_HELD ] = {
	.pme_name = "PM_CLB_HELD",
	.pme_code = 0x000000208C,
	.pme_short_desc = "CLB (control logic block - indicates quadword fetch block) Hold: Any Reason",
	.pme_long_desc = "CLB (control logic block - indicates quadword fetch block) Hold: Any Reason",
},
[ POWER9_PME_PM_CMPLU_STALL_ANY_SYNC ] = {
	.pme_name = "PM_CMPLU_STALL_ANY_SYNC",
	.pme_code = 0x000001E05A,
	.pme_short_desc = "Cycles in which the NTC sync instruction (isync, lwsync or hwsync) is not allowed to complete",
	.pme_long_desc = "Cycles in which the NTC sync instruction (isync, lwsync or hwsync) is not allowed to complete",
},
[ POWER9_PME_PM_CMPLU_STALL_BRU ] = {
	.pme_name = "PM_CMPLU_STALL_BRU",
	.pme_code = 0x000004D018,
	.pme_short_desc = "Completion stall due to a Branch Unit",
	.pme_long_desc = "Completion stall due to a Branch Unit",
},
[ POWER9_PME_PM_CMPLU_STALL_CRYPTO ] = {
	.pme_name = "PM_CMPLU_STALL_CRYPTO",
	.pme_code = 0x000004C01E,
	.pme_short_desc = "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish",
	.pme_long_desc = "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish",
},
[ POWER9_PME_PM_CMPLU_STALL_DCACHE_MISS ] = {
	.pme_name = "PM_CMPLU_STALL_DCACHE_MISS",
	.pme_code = 0x000002C012,
	.pme_short_desc = "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest",
	.pme_long_desc = "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest",
},
[ POWER9_PME_PM_CMPLU_STALL_DFLONG ] = {
	.pme_name = "PM_CMPLU_STALL_DFLONG",
	.pme_code = 0x000001005A,
	.pme_short_desc = "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish.",
	.pme_long_desc = "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Qualified by multicycle",
},
[ POWER9_PME_PM_CMPLU_STALL_DFU ] = {
	.pme_name = "PM_CMPLU_STALL_DFU",
	.pme_code = 0x000002D012,
	.pme_short_desc = "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish.",
	.pme_long_desc = "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Not qualified by multicycle",
},
[ POWER9_PME_PM_CMPLU_STALL_DMISS_L21_L31 ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_L21_L31",
	.pme_code = 0x000002C018,
	.pme_short_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
	.pme_long_desc = "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
},
[ POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3_CONFLICT ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
	.pme_code = 0x000004C016,
	.pme_short_desc = "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
	.pme_long_desc = "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
},
[ POWER9_PME_PM_CMPLU_STALL_DMISS_L2L3 ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_L2L3",
	.pme_code = 0x000001003C,
	.pme_short_desc = "Completion stall by Dcache miss which resolved in L2/L3",
	.pme_long_desc = "Completion stall by Dcache miss which resolved in L2/L3",
},
[ POWER9_PME_PM_CMPLU_STALL_DMISS_L3MISS ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_L3MISS",
	.pme_code = 0x000004C01A,
	.pme_short_desc = "Completion stall due to cache miss resolving missed the L3",
	.pme_long_desc = "Completion stall due to cache miss resolving missed the L3",
},
[ POWER9_PME_PM_CMPLU_STALL_DMISS_LMEM ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_LMEM",
	.pme_code = 0x0000030038,
	.pme_short_desc = "Completion stall due to cache miss that resolves in local memory",
	.pme_long_desc = "Completion stall due to cache miss that resolves in local memory",
},
[ POWER9_PME_PM_CMPLU_STALL_DMISS_REMOTE ] = {
	.pme_name = "PM_CMPLU_STALL_DMISS_REMOTE",
	.pme_code = 0x000002C01C,
	.pme_short_desc = "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
	.pme_long_desc = "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
},
[ POWER9_PME_PM_CMPLU_STALL_DPLONG ] = {
	.pme_name = "PM_CMPLU_STALL_DPLONG",
	.pme_code = 0x000003405C,
	.pme_short_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish.",
	.pme_long_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle",
},
[ POWER9_PME_PM_CMPLU_STALL_DP ] = {
	.pme_name = "PM_CMPLU_STALL_DP",
	.pme_code = 0x000001005C,
	.pme_short_desc = "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish.",
	.pme_long_desc = "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by NOT vector",
},
[ POWER9_PME_PM_CMPLU_STALL_EIEIO ] = {
	.pme_name = "PM_CMPLU_STALL_EIEIO",
	.pme_code = 0x000004D01A,
	.pme_short_desc = "Finish stall because the NTF instruction is an EIEIO waiting for response from L2",
	.pme_long_desc = "Finish stall because the NTF instruction is an EIEIO waiting for response from L2",
},
[ POWER9_PME_PM_CMPLU_STALL_EMQ_FULL ] = {
	.pme_name = "PM_CMPLU_STALL_EMQ_FULL",
	.pme_code = 0x0000030004,
	.pme_short_desc = "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full",
	.pme_long_desc = "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full",
},
[ POWER9_PME_PM_CMPLU_STALL_ERAT_MISS ] = {
	.pme_name = "PM_CMPLU_STALL_ERAT_MISS",
	.pme_code = 0x000004C012,
	.pme_short_desc = "Finish stall because the NTF instruction was a load or store that suffered a translation miss",
	.pme_long_desc = "Finish stall because the NTF instruction was a load or store that suffered a translation miss",
},
[ POWER9_PME_PM_CMPLU_STALL_EXCEPTION ] = {
	.pme_name = "PM_CMPLU_STALL_EXCEPTION",
	.pme_code = 0x000003003A,
	.pme_short_desc = "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete",
	.pme_long_desc = "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete",
},
[ POWER9_PME_PM_CMPLU_STALL_EXEC_UNIT ] = {
	.pme_name = "PM_CMPLU_STALL_EXEC_UNIT",
	.pme_code = 0x000002D018,
	.pme_short_desc = "Completion stall due to execution units (FXU/VSU/CRU)",
	.pme_long_desc = "Completion stall due to execution units (FXU/VSU/CRU)",
},
[ POWER9_PME_PM_CMPLU_STALL_FLUSH_ANY_THREAD ] = {
	.pme_name = "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
	.pme_code = 0x000001E056,
	.pme_short_desc = "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion",
	.pme_long_desc = "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion",
},
[ POWER9_PME_PM_CMPLU_STALL_FXLONG ] = {
	.pme_name = "PM_CMPLU_STALL_FXLONG",
	.pme_code = 0x000004D016,
	.pme_short_desc = "Completion stall due to a long latency scalar fixed point instruction (division, square root)",
	.pme_long_desc = "Completion stall due to a long latency scalar fixed point instruction (division, square root)",
},
[ POWER9_PME_PM_CMPLU_STALL_FXU ] = {
	.pme_name = "PM_CMPLU_STALL_FXU",
	.pme_code = 0x000002D016,
	.pme_short_desc = "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline.",
	.pme_long_desc = "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
},
[ POWER9_PME_PM_CMPLU_STALL_HWSYNC ] = {
	.pme_name = "PM_CMPLU_STALL_HWSYNC",
	.pme_code = 0x0000030036,
	.pme_short_desc = "completion stall due to hwsync",
	.pme_long_desc = "completion stall due to hwsync",
},
[ POWER9_PME_PM_CMPLU_STALL_LARX ] = {
	.pme_name = "PM_CMPLU_STALL_LARX",
	.pme_code = 0x000001002A,
	.pme_short_desc = "Finish stall because the NTF instruction was a larx waiting to be satisfied",
	.pme_long_desc = "Finish stall because the NTF instruction was a larx waiting to be satisfied",
},
[ POWER9_PME_PM_CMPLU_STALL_LHS ] = {
	.pme_name = "PM_CMPLU_STALL_LHS",
	.pme_code = 0x000002C01A,
	.pme_short_desc = "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data",
	.pme_long_desc = "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data",
},
[ POWER9_PME_PM_CMPLU_STALL_LMQ_FULL ] = {
	.pme_name = "PM_CMPLU_STALL_LMQ_FULL",
	.pme_code = 0x000004C014,
	.pme_short_desc = "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full",
	.pme_long_desc = "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full",
},
[ POWER9_PME_PM_CMPLU_STALL_LOAD_FINISH ] = {
	.pme_name = "PM_CMPLU_STALL_LOAD_FINISH",
	.pme_code = 0x000004D014,
	.pme_short_desc = "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish",
	.pme_long_desc = "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish",
},
[ POWER9_PME_PM_CMPLU_STALL_LRQ_FULL ] = {
	.pme_name = "PM_CMPLU_STALL_LRQ_FULL",
	.pme_code = 0x000002D014,
	.pme_short_desc = "Finish stall because the NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-reorder queue) was full",
	.pme_long_desc = "Finish stall because the NTF instruction was a load that was held in LSAQ (load-store address queue) because the LRQ (load-reorder queue) was full",
},
[ POWER9_PME_PM_CMPLU_STALL_LRQ_OTHER ] = {
	.pme_name = "PM_CMPLU_STALL_LRQ_OTHER",
	.pme_code = 0x0000010004,
	.pme_short_desc = "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others",
	.pme_long_desc = "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others",
},
[ POWER9_PME_PM_CMPLU_STALL_LSAQ_ARB ] = {
	.pme_name = "PM_CMPLU_STALL_LSAQ_ARB",
	.pme_code = 0x000004E016,
	.pme_short_desc = "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch",
	.pme_long_desc = "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch",
},
[ POWER9_PME_PM_CMPLU_STALL_LSU_FIN ] = {
	.pme_name = "PM_CMPLU_STALL_LSU_FIN",
	.pme_code = 0x000001003A,
	.pme_short_desc = "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish",
	.pme_long_desc = "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish",
},
[ POWER9_PME_PM_CMPLU_STALL_LSU_FLUSH_NEXT ] = {
	.pme_name = "PM_CMPLU_STALL_LSU_FLUSH_NEXT",
	.pme_code = 0x000002E01A,
	.pme_short_desc = "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence.",
	.pme_long_desc = "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete",
},
[ POWER9_PME_PM_CMPLU_STALL_LSU_MFSPR ] = {
	.pme_name = "PM_CMPLU_STALL_LSU_MFSPR",
	.pme_code = 0x0000034056,
	.pme_short_desc = "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned",
	.pme_long_desc = "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned",
},
[ POWER9_PME_PM_CMPLU_STALL_LSU ] = {
	.pme_name = "PM_CMPLU_STALL_LSU",
	.pme_code = 0x000002C010,
	.pme_short_desc = "Completion stall by LSU instruction",
	.pme_long_desc = "Completion stall by LSU instruction",
},
[ POWER9_PME_PM_CMPLU_STALL_LWSYNC ] = {
	.pme_name = "PM_CMPLU_STALL_LWSYNC",
	.pme_code = 0x0000010036,
	.pme_short_desc = "completion stall due to lwsync",
	.pme_long_desc = "completion stall due to lwsync",
},
[ POWER9_PME_PM_CMPLU_STALL_MTFPSCR ] = {
	.pme_name = "PM_CMPLU_STALL_MTFPSCR",
	.pme_code = 0x000004E012,
	.pme_short_desc = "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)",
	.pme_long_desc = "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)",
},
[ POWER9_PME_PM_CMPLU_STALL_NESTED_TBEGIN ] = {
	.pme_name = "PM_CMPLU_STALL_NESTED_TBEGIN",
	.pme_code = 0x000001E05C,
	.pme_short_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin.",
	.pme_long_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tbegin. This is a short delay, and it includes ROT",
},
[ POWER9_PME_PM_CMPLU_STALL_NESTED_TEND ] = {
	.pme_name = "PM_CMPLU_STALL_NESTED_TEND",
	.pme_code = 0x000003003C,
	.pme_short_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level.",
	.pme_long_desc = "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level. This is a short delay",
},
[ POWER9_PME_PM_CMPLU_STALL_NTC_DISP_FIN ] = {
	.pme_name = "PM_CMPLU_STALL_NTC_DISP_FIN",
	.pme_code = 0x000004E018,
	.pme_short_desc = "Finish stall because the NTF instruction was one that must finish at dispatch.",
	.pme_long_desc = "Finish stall because the NTF instruction was one that must finish at dispatch.",
},
[ POWER9_PME_PM_CMPLU_STALL_NTC_FLUSH ] = {
	.pme_name = "PM_CMPLU_STALL_NTC_FLUSH",
	.pme_code = 0x000002E01E,
	.pme_short_desc = "Completion stall due to ntc flush",
	.pme_long_desc = "Completion stall due to ntc flush",
},
[ POWER9_PME_PM_CMPLU_STALL_OTHER_CMPL ] = {
	.pme_name = "PM_CMPLU_STALL_OTHER_CMPL",
	.pme_code = 0x0000030006,
	.pme_short_desc = "Instructions the core completed while this tread was stalled",
	.pme_long_desc = "Instructions the core completed while this tread was stalled",
},
[ POWER9_PME_PM_CMPLU_STALL_PASTE ] = {
	.pme_name = "PM_CMPLU_STALL_PASTE",
	.pme_code = 0x000002C016,
	.pme_short_desc = "Finish stall because the NTF instruction was a paste waiting for response from L2",
	.pme_long_desc = "Finish stall because the NTF instruction was a paste waiting for response from L2",
},
[ POWER9_PME_PM_CMPLU_STALL_PM ] = {
	.pme_name = "PM_CMPLU_STALL_PM",
	.pme_code = 0x000003000A,
	.pme_short_desc = "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish.",
	.pme_long_desc = "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish. Includes permute and decimal fixed point instructions (128 bit BCD arithmetic) + a few 128 bit fixpoint add/subtract instructions with carry. Not qualified by vector or multicycle",
},
[ POWER9_PME_PM_CMPLU_STALL_SLB ] = {
	.pme_name = "PM_CMPLU_STALL_SLB",
	.pme_code = 0x000001E052,
	.pme_short_desc = "Finish stall because the NTF instruction was awaiting L2 response for an SLB",
	.pme_long_desc = "Finish stall because the NTF instruction was awaiting L2 response for an SLB",
},
[ POWER9_PME_PM_CMPLU_STALL_SPEC_FINISH ] = {
	.pme_name = "PM_CMPLU_STALL_SPEC_FINISH",
	.pme_code = 0x0000030028,
	.pme_short_desc = "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC",
	.pme_long_desc = "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC",
},
[ POWER9_PME_PM_CMPLU_STALL_SRQ_FULL ] = {
	.pme_name = "PM_CMPLU_STALL_SRQ_FULL",
	.pme_code = 0x0000030016,
	.pme_short_desc = "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full",
	.pme_long_desc = "Finish stall because the NTF instruction was a store that was held in LSAQ because the SRQ was full",
},
[ POWER9_PME_PM_CMPLU_STALL_STCX ] = {
	.pme_name = "PM_CMPLU_STALL_STCX",
	.pme_code = 0x000002D01C,
	.pme_short_desc = "Finish stall because the NTF instruction was a stcx waiting for response from L2",
	.pme_long_desc = "Finish stall because the NTF instruction was a stcx waiting for response from L2",
},
[ POWER9_PME_PM_CMPLU_STALL_ST_FWD ] = {
	.pme_name = "PM_CMPLU_STALL_ST_FWD",
	.pme_code = 0x000004C01C,
	.pme_short_desc = "Completion stall due to store forward",
	.pme_long_desc = "Completion stall due to store forward",
},
[ POWER9_PME_PM_CMPLU_STALL_STORE_DATA ] = {
	.pme_name = "PM_CMPLU_STALL_STORE_DATA",
	.pme_code = 0x0000030026,
	.pme_short_desc = "Finish stall because the next to finish instruction was a store waiting on data",
	.pme_long_desc = "Finish stall because the next to finish instruction was a store waiting on data",
},
[ POWER9_PME_PM_CMPLU_STALL_STORE_FIN_ARB ] = {
	.pme_name = "PM_CMPLU_STALL_STORE_FIN_ARB",
	.pme_code = 0x0000030014,
	.pme_short_desc = "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe.",
	.pme_long_desc = "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe",
},
[ POWER9_PME_PM_CMPLU_STALL_STORE_FINISH ] = {
	.pme_name = "PM_CMPLU_STALL_STORE_FINISH",
	.pme_code = 0x000002C014,
	.pme_short_desc = "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish",
	.pme_long_desc = "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish",
},
[ POWER9_PME_PM_CMPLU_STALL_STORE_PIPE_ARB ] = {
	.pme_name = "PM_CMPLU_STALL_STORE_PIPE_ARB",
	.pme_code = 0x000004C010,
	.pme_short_desc = "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject.",
	.pme_long_desc = "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration",
},
[ POWER9_PME_PM_CMPLU_STALL_SYNC_PMU_INT ] = {
	.pme_name = "PM_CMPLU_STALL_SYNC_PMU_INT",
	.pme_code = 0x000002C01E,
	.pme_short_desc = "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt",
	.pme_long_desc = "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt",
},
[ POWER9_PME_PM_CMPLU_STALL_TEND ] = {
	.pme_name = "PM_CMPLU_STALL_TEND",
	.pme_code = 0x000001E050,
	.pme_short_desc = "Finish stall because the NTF instruction was a tend instruction awaiting response from L2",
	.pme_long_desc = "Finish stall because the NTF instruction was a tend instruction awaiting response from L2",
},
[ POWER9_PME_PM_CMPLU_STALL_THRD ] = {
	.pme_name = "PM_CMPLU_STALL_THRD",
	.pme_code = 0x000001001C,
	.pme_short_desc = "Completion Stalled because the thread was blocked",
	.pme_long_desc = "Completion Stalled because the thread was blocked",
},
[ POWER9_PME_PM_CMPLU_STALL_TLBIE ] = {
	.pme_name = "PM_CMPLU_STALL_TLBIE",
	.pme_code = 0x000002E01C,
	.pme_short_desc = "Finish stall because the NTF instruction was a tlbie waiting for response from L2",
	.pme_long_desc = "Finish stall because the NTF instruction was a tlbie waiting for response from L2",
},
[ POWER9_PME_PM_CMPLU_STALL ] = {
	.pme_name = "PM_CMPLU_STALL",
	.pme_code = 0x000001E054,
	.pme_short_desc = "Nothing completed and ICT not empty",
	.pme_long_desc = "Nothing completed and ICT not empty",
},
[ POWER9_PME_PM_CMPLU_STALL_VDPLONG ] = {
	.pme_name = "PM_CMPLU_STALL_VDPLONG",
	.pme_code = 0x000003C05A,
	.pme_short_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish.",
	.pme_long_desc = "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle",
},
[ POWER9_PME_PM_CMPLU_STALL_VDP ] = {
	.pme_name = "PM_CMPLU_STALL_VDP",
	.pme_code = 0x000004405C,
	.pme_short_desc = "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish.",
	.pme_long_desc = "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector",
},
[ POWER9_PME_PM_CMPLU_STALL_VFXLONG ] = {
	.pme_name = "PM_CMPLU_STALL_VFXLONG",
	.pme_code = 0x000002E018,
	.pme_short_desc = "Completion stall due to a long latency vector fixed point instruction (division, square root)",
	.pme_long_desc = "Completion stall due to a long latency vector fixed point instruction (division, square root)",
},
[ POWER9_PME_PM_CMPLU_STALL_VFXU ] = {
	.pme_name = "PM_CMPLU_STALL_VFXU",
	.pme_code = 0x000003C05C,
	.pme_short_desc = "Finish stall due to a vector fixed point instruction in the execution pipeline.",
	.pme_long_desc = "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
},
[ POWER9_PME_PM_CO0_BUSY ] = {
	.pme_name = "PM_CO0_BUSY",
	.pme_code = 0x000003608C,
	.pme_short_desc = "CO mach 0 Busy.",
	.pme_long_desc = "CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point)",
},
[ POWER9_PME_PM_CO0_BUSY_ALT ] = {
	.pme_name = "PM_CO0_BUSY_ALT",
	.pme_code = 0x000004608C,
	.pme_short_desc = "CO mach 0 Busy.",
	.pme_long_desc = "CO mach 0 Busy. Used by PMU to sample ave CO lifetime (mach0 used as sample point)",
},
[ POWER9_PME_PM_CO_DISP_FAIL ] = {
	.pme_name = "PM_CO_DISP_FAIL",
	.pme_code = 0x0000016886,
	.pme_short_desc = "CO dispatch failed due to all CO machines being busy",
	.pme_long_desc = "CO dispatch failed due to all CO machines being busy",
},
[ POWER9_PME_PM_CO_TM_SC_FOOTPRINT ] = {
	.pme_name = "PM_CO_TM_SC_FOOTPRINT",
	.pme_code = 0x0000026086,
	.pme_short_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L3 indicated SC line formed in L3 on RDR bus",
	.pme_long_desc = "L2 did a cleanifdirty CO to the L3 (ie created an SC line in the L3) OR L2 TM_store hit dirty HPC line and L3 indicated SC line formed in L3 on RDR bus",
},
[ POWER9_PME_PM_CO_USAGE ] = {
	.pme_name = "PM_CO_USAGE",
	.pme_code = 0x000002688C,
	.pme_short_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy.",
	.pme_long_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running",
},
/* See also alternate entries for 000001001E / POWER9_PME_PM_CYC with code(s) 000002001E 000003001E 000004001E at the bottom of this table. \n */
[ POWER9_PME_PM_CYC ] = {
	.pme_name = "PM_CYC",
	.pme_code = 0x000001001E,
	.pme_short_desc = "Processor cycles",
	.pme_long_desc = "Processor cycles",
},
[ POWER9_PME_PM_DARQ0_0_3_ENTRIES ] = {
	.pme_name = "PM_DARQ0_0_3_ENTRIES",
	.pme_code = 0x000004D04A,
	.pme_short_desc = "Cycles in which 3 or less DARQ entries (out of 12) are in use",
	.pme_long_desc = "Cycles in which 3 or less DARQ entries (out of 12) are in use",
},
[ POWER9_PME_PM_DARQ0_10_12_ENTRIES ] = {
	.pme_name = "PM_DARQ0_10_12_ENTRIES",
	.pme_code = 0x000001D058,
	.pme_short_desc = "Cycles in which 10 or more DARQ entries (out of 12) are in use",
	.pme_long_desc = "Cycles in which 10 or more DARQ entries (out of 12) are in use",
},
[ POWER9_PME_PM_DARQ0_4_6_ENTRIES ] = {
	.pme_name = "PM_DARQ0_4_6_ENTRIES",
	.pme_code = 0x000003504E,
	.pme_short_desc = "Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use",
	.pme_long_desc = "Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use",
},
[ POWER9_PME_PM_DARQ0_7_9_ENTRIES ] = {
	.pme_name = "PM_DARQ0_7_9_ENTRIES",
	.pme_code = 0x000002E050,
	.pme_short_desc = "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use",
	.pme_long_desc = "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use",
},
[ POWER9_PME_PM_DARQ1_0_3_ENTRIES ] = {
	.pme_name = "PM_DARQ1_0_3_ENTRIES",
	.pme_code = 0x000004C122,
	.pme_short_desc = "Cycles in which 3 or fewer DARQ1 entries (out of 12) are in use",
	.pme_long_desc = "Cycles in which 3 or fewer DARQ1 entries (out of 12) are in use",
},
[ POWER9_PME_PM_DARQ1_10_12_ENTRIES ] = {
	.pme_name = "PM_DARQ1_10_12_ENTRIES",
	.pme_code = 0x0000020058,
	.pme_short_desc = "Cycles in which 10 or more DARQ1 entries (out of 12) are in use",
	.pme_long_desc = "Cycles in which 10 or more DARQ1 entries (out of 12) are in use",
},
[ POWER9_PME_PM_DARQ1_4_6_ENTRIES ] = {
	.pme_name = "PM_DARQ1_4_6_ENTRIES",
	.pme_code = 0x000003E050,
	.pme_short_desc = "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use",
	.pme_long_desc = "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use",
},
[ POWER9_PME_PM_DARQ1_7_9_ENTRIES ] = {
	.pme_name = "PM_DARQ1_7_9_ENTRIES",
	.pme_code = 0x000002005A,
	.pme_short_desc = "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use",
	.pme_long_desc = "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use",
},
[ POWER9_PME_PM_DARQ_STORE_REJECT ] = {
	.pme_name = "PM_DARQ_STORE_REJECT",
	.pme_code = 0x000004405E,
	.pme_short_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected.",
	.pme_long_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected. Divide by PM_DARQ_STORE_XMIT to get reject ratio",
},
[ POWER9_PME_PM_DARQ_STORE_XMIT ] = {
	.pme_name = "PM_DARQ_STORE_XMIT",
	.pme_code = 0x0000030064,
	.pme_short_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry.",
	.pme_long_desc = "The DARQ attempted to transmit a store into an LSAQ or SRQ entry. Includes rejects. Not qualified by thread, so it includes counts for the whole core",
},
[ POWER9_PME_PM_DATA_CHIP_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_CHIP_PUMP_CPRED",
	.pme_code = 0x000001C050,
	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
	.pme_long_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
},
[ POWER9_PME_PM_DATA_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_DATA_FROM_DL2L3_MOD",
	.pme_code = 0x000004C048,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_DATA_FROM_DL2L3_SHR",
	.pme_code = 0x000003C048,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_DL4 ] = {
	.pme_name = "PM_DATA_FROM_DL4",
	.pme_code = 0x000003C04C,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_DMEM ] = {
	.pme_name = "PM_DATA_FROM_DMEM",
	.pme_code = 0x000004C04C,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L21_MOD ] = {
	.pme_name = "PM_DATA_FROM_L21_MOD",
	.pme_code = 0x000004C046,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L21_SHR ] = {
	.pme_name = "PM_DATA_FROM_L21_SHR",
	.pme_code = 0x000003C046,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x000003C040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x000004C040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L2_MEPF ] = {
	.pme_name = "PM_DATA_FROM_L2_MEPF",
	.pme_code = 0x000002C040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L2MISS_MOD ] = {
	.pme_name = "PM_DATA_FROM_L2MISS_MOD",
	.pme_code = 0x000001C04E,
	.pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L2MISS ] = {
	.pme_name = "PM_DATA_FROM_L2MISS",
	.pme_code = 0x00000200FE,
	.pme_short_desc = "Demand LD - L2 Miss (not L2 hit)",
	.pme_long_desc = "Demand LD - L2 Miss (not L2 hit)",
},
[ POWER9_PME_PM_DATA_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_DATA_FROM_L2_NO_CONFLICT",
	.pme_code = 0x000001C040,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L2 ] = {
	.pme_name = "PM_DATA_FROM_L2",
	.pme_code = 0x000001C042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_DATA_FROM_L31_ECO_MOD",
	.pme_code = 0x000004C044,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_DATA_FROM_L31_ECO_SHR",
	.pme_code = 0x000003C044,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L31_MOD ] = {
	.pme_name = "PM_DATA_FROM_L31_MOD",
	.pme_code = 0x000002C044,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L31_SHR ] = {
	.pme_name = "PM_DATA_FROM_L31_SHR",
	.pme_code = 0x000001C046,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_DATA_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x000003C042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L3_MEPF ] = {
	.pme_name = "PM_DATA_FROM_L3_MEPF",
	.pme_code = 0x000002C042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L3MISS_MOD ] = {
	.pme_name = "PM_DATA_FROM_L3MISS_MOD",
	.pme_code = 0x000004C04E,
	.pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L3MISS ] = {
	.pme_name = "PM_DATA_FROM_L3MISS",
	.pme_code = 0x00000300FE,
	.pme_short_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
	.pme_long_desc = "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
},
[ POWER9_PME_PM_DATA_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_DATA_FROM_L3_NO_CONFLICT",
	.pme_code = 0x000001C044,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_L3 ] = {
	.pme_name = "PM_DATA_FROM_L3",
	.pme_code = 0x000004C042,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_LL4 ] = {
	.pme_name = "PM_DATA_FROM_LL4",
	.pme_code = 0x000001C04C,
	.pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_LMEM ] = {
	.pme_name = "PM_DATA_FROM_LMEM",
	.pme_code = 0x000002C048,
	.pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_MEMORY ] = {
	.pme_name = "PM_DATA_FROM_MEMORY",
	.pme_code = 0x00000400FE,
	.pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_DATA_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x000004C04A,
	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_DATA_FROM_ON_CHIP_CACHE",
	.pme_code = 0x000001C048,
	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_DATA_FROM_RL2L3_MOD",
	.pme_code = 0x000002C046,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_DATA_FROM_RL2L3_SHR",
	.pme_code = 0x000001C04A,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_RL4 ] = {
	.pme_name = "PM_DATA_FROM_RL4",
	.pme_code = 0x000002C04A,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
},
[ POWER9_PME_PM_DATA_FROM_RMEM ] = {
	.pme_name = "PM_DATA_FROM_RMEM",
	.pme_code = 0x000003C04A,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
},
[ POWER9_PME_PM_DATA_GRP_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_GRP_PUMP_CPRED",
	.pme_code = 0x000002C050,
	.pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
	.pme_long_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for a demand load",
},
[ POWER9_PME_PM_DATA_GRP_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_DATA_GRP_PUMP_MPRED_RTY",
	.pme_code = 0x000001C052,
	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
	.pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
},
[ POWER9_PME_PM_DATA_GRP_PUMP_MPRED ] = {
	.pme_name = "PM_DATA_GRP_PUMP_MPRED",
	.pme_code = 0x000002C052,
	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load",
	.pme_long_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load",
},
[ POWER9_PME_PM_DATA_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_PUMP_CPRED",
	.pme_code = 0x000001C054,
	.pme_short_desc = "Pump prediction correct.",
	.pme_long_desc = "Pump prediction correct. Counts across all types of pumps for a demand load",
},
[ POWER9_PME_PM_DATA_PUMP_MPRED ] = {
	.pme_name = "PM_DATA_PUMP_MPRED",
	.pme_code = 0x000004C052,
	.pme_short_desc = "Pump misprediction.",
	.pme_long_desc = "Pump misprediction. Counts across all types of pumps for a demand load",
},
[ POWER9_PME_PM_DATA_STORE ] = {
	.pme_name = "PM_DATA_STORE",
	.pme_code = 0x000000F0A0,
	.pme_short_desc = "All ops that drain from s2q to L2 containing data",
	.pme_long_desc = "All ops that drain from s2q to L2 containing data",
},
[ POWER9_PME_PM_DATA_SYS_PUMP_CPRED ] = {
	.pme_name = "PM_DATA_SYS_PUMP_CPRED",
	.pme_code = 0x000003C050,
	.pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load",
	.pme_long_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load",
},
[ POWER9_PME_PM_DATA_SYS_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_DATA_SYS_PUMP_MPRED_RTY",
	.pme_code = 0x000004C050,
	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load",
	.pme_long_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load",
},
[ POWER9_PME_PM_DATA_SYS_PUMP_MPRED ] = {
	.pme_name = "PM_DATA_SYS_PUMP_MPRED",
	.pme_code = 0x000003C052,
	.pme_short_desc = "Final Pump Scope (system) mispredicted.",
	.pme_long_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load",
},
[ POWER9_PME_PM_DATA_TABLEWALK_CYC ] = {
	.pme_name = "PM_DATA_TABLEWALK_CYC",
	.pme_code = 0x000003001A,
	.pme_short_desc = "Data Tablewalk Cycles.",
	.pme_long_desc = "Data Tablewalk Cycles. Could be 1 or 2 active tablewalks. Includes data prefetches.",
},
[ POWER9_PME_PM_DC_DEALLOC_NO_CONF ] = {
	.pme_name = "PM_DC_DEALLOC_NO_CONF",
	.pme_code = 0x000000F8AC,
	.pme_short_desc = "A demand load referenced a line in an active fuzzy prefetch stream.",
	.pme_long_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)",
},
[ POWER9_PME_PM_DC_PREF_CONF ] = {
	.pme_name = "PM_DC_PREF_CONF",
	.pme_code = 0x000000F0A8,
	.pme_short_desc = "A demand load referenced a line in an active prefetch stream.",
	.pme_long_desc = "A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Includes forwards and backwards streams",
},
[ POWER9_PME_PM_DC_PREF_CONS_ALLOC ] = {
	.pme_name = "PM_DC_PREF_CONS_ALLOC",
	.pme_code = 0x000000F0B4,
	.pme_short_desc = "Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch",
	.pme_long_desc = "Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch",
},
[ POWER9_PME_PM_DC_PREF_FUZZY_CONF ] = {
	.pme_name = "PM_DC_PREF_FUZZY_CONF",
	.pme_code = 0x000000F8A8,
	.pme_short_desc = "A demand load referenced a line in an active fuzzy prefetch stream.",
	.pme_long_desc = "A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up)",
},
[ POWER9_PME_PM_DC_PREF_HW_ALLOC ] = {
	.pme_name = "PM_DC_PREF_HW_ALLOC",
	.pme_code = 0x000000F0A4,
	.pme_short_desc = "Prefetch stream allocated by the hardware prefetch mechanism",
	.pme_long_desc = "Prefetch stream allocated by the hardware prefetch mechanism",
},
[ POWER9_PME_PM_DC_PREF_STRIDED_CONF ] = {
	.pme_name = "PM_DC_PREF_STRIDED_CONF",
	.pme_code = 0x000000F0AC,
	.pme_short_desc = "A demand load referenced a line in an active strided prefetch stream.",
	.pme_long_desc = "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.",
},
[ POWER9_PME_PM_DC_PREF_SW_ALLOC ] = {
	.pme_name = "PM_DC_PREF_SW_ALLOC",
	.pme_code = 0x000000F8A4,
	.pme_short_desc = "Prefetch stream allocated by software prefetching",
	.pme_long_desc = "Prefetch stream allocated by software prefetching",
},
[ POWER9_PME_PM_DC_PREF_XCONS_ALLOC ] = {
	.pme_name = "PM_DC_PREF_XCONS_ALLOC",
	.pme_code = 0x000000F8B4,
	.pme_short_desc = "Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch",
	.pme_long_desc = "Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch",
},
[ POWER9_PME_PM_DECODE_FUSION_CONST_GEN ] = {
	.pme_name = "PM_DECODE_FUSION_CONST_GEN",
	.pme_code = 0x00000048B4,
	.pme_short_desc = "32-bit constant generation",
	.pme_long_desc = "32-bit constant generation",
},
[ POWER9_PME_PM_DECODE_FUSION_EXT_ADD ] = {
	.pme_name = "PM_DECODE_FUSION_EXT_ADD",
	.pme_code = 0x0000005084,
	.pme_short_desc = "32-bit extended addition",
	.pme_long_desc = "32-bit extended addition",
},
[ POWER9_PME_PM_DECODE_FUSION_LD_ST_DISP ] = {
	.pme_name = "PM_DECODE_FUSION_LD_ST_DISP",
	.pme_code = 0x00000048A8,
	.pme_short_desc = "32-bit displacement D-form and 16-bit displacement X-form",
	.pme_long_desc = "32-bit displacement D-form and 16-bit displacement X-form",
},
[ POWER9_PME_PM_DECODE_FUSION_OP_PRESERV ] = {
	.pme_name = "PM_DECODE_FUSION_OP_PRESERV",
	.pme_code = 0x0000005088,
	.pme_short_desc = "Destructive op operand preservation",
	.pme_long_desc = "Destructive op operand preservation",
},
[ POWER9_PME_PM_DECODE_HOLD_ICT_FULL ] = {
	.pme_name = "PM_DECODE_HOLD_ICT_FULL",
	.pme_code = 0x00000058A8,
	.pme_short_desc = "Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use.",
	.pme_long_desc = "Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread",
},
[ POWER9_PME_PM_DECODE_LANES_NOT_AVAIL ] = {
	.pme_name = "PM_DECODE_LANES_NOT_AVAIL",
	.pme_code = 0x0000005884,
	.pme_short_desc = "Decode has something to transmit but dispatch lanes are not available",
	.pme_long_desc = "Decode has something to transmit but dispatch lanes are not available",
},
[ POWER9_PME_PM_DERAT_MISS_16G ] = {
	.pme_name = "PM_DERAT_MISS_16G",
	.pme_code = 0x000004C054,
	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16G",
	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16G",
},
[ POWER9_PME_PM_DERAT_MISS_16M ] = {
	.pme_name = "PM_DERAT_MISS_16M",
	.pme_code = 0x000003C054,
	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 16M",
	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 16M",
},
[ POWER9_PME_PM_DERAT_MISS_1G ] = {
	.pme_name = "PM_DERAT_MISS_1G",
	.pme_code = 0x000002C05A,
	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 1G.",
	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation",
},
[ POWER9_PME_PM_DERAT_MISS_2M ] = {
	.pme_name = "PM_DERAT_MISS_2M",
	.pme_code = 0x000001C05A,
	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 2M.",
	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation",
},
[ POWER9_PME_PM_DERAT_MISS_4K ] = {
	.pme_name = "PM_DERAT_MISS_4K",
	.pme_code = 0x000001C056,
	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 4K",
	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 4K",
},
[ POWER9_PME_PM_DERAT_MISS_64K ] = {
	.pme_name = "PM_DERAT_MISS_64K",
	.pme_code = 0x000002C054,
	.pme_short_desc = "Data ERAT Miss (Data TLB Access) page size 64K",
	.pme_long_desc = "Data ERAT Miss (Data TLB Access) page size 64K",
},
[ POWER9_PME_PM_DFU_BUSY ] = {
	.pme_name = "PM_DFU_BUSY",
	.pme_code = 0x000004D04C,
	.pme_short_desc = "Cycles in which all 4 Decimal Floating Point units are busy.",
	.pme_long_desc = "Cycles in which all 4 Decimal Floating Point units are busy. The DFU is running at capacity",
},
[ POWER9_PME_PM_DISP_CLB_HELD_BAL ] = {
	.pme_name = "PM_DISP_CLB_HELD_BAL",
	.pme_code = 0x000000288C,
	.pme_short_desc = "Dispatch/CLB Hold: Balance Flush",
	.pme_long_desc = "Dispatch/CLB Hold: Balance Flush",
},
[ POWER9_PME_PM_DISP_CLB_HELD_SB ] = {
	.pme_name = "PM_DISP_CLB_HELD_SB",
	.pme_code = 0x0000002090,
	.pme_short_desc = "Dispatch/CLB Hold: Scoreboard",
	.pme_long_desc = "Dispatch/CLB Hold: Scoreboard",
},
[ POWER9_PME_PM_DISP_CLB_HELD_TLBIE ] = {
	.pme_name = "PM_DISP_CLB_HELD_TLBIE",
	.pme_code = 0x0000002890,
	.pme_short_desc = "Dispatch Hold: Due to TLBIE",
	.pme_long_desc = "Dispatch Hold: Due to TLBIE",
},
[ POWER9_PME_PM_DISP_HELD_HB_FULL ] = {
	.pme_name = "PM_DISP_HELD_HB_FULL",
	.pme_code = 0x000003D05C,
	.pme_short_desc = "Dispatch held due to History Buffer full.",
	.pme_long_desc = "Dispatch held due to History Buffer full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)",
},
[ POWER9_PME_PM_DISP_HELD_ISSQ_FULL ] = {
	.pme_name = "PM_DISP_HELD_ISSQ_FULL",
	.pme_code = 0x0000020006,
	.pme_short_desc = "Dispatch held due to Issue q full.",
	.pme_long_desc = "Dispatch held due to Issue q full. Includes issue queue and branch queue",
},
[ POWER9_PME_PM_DISP_HELD_SYNC_HOLD ] = {
	.pme_name = "PM_DISP_HELD_SYNC_HOLD",
	.pme_code = 0x000004003C,
	.pme_short_desc = "Cycles in which dispatch is held because of a synchronizing instruction in the pipeline",
	.pme_long_desc = "Cycles in which dispatch is held because of a synchronizing instruction in the pipeline",
},
[ POWER9_PME_PM_DISP_HELD_TBEGIN ] = {
	.pme_name = "PM_DISP_HELD_TBEGIN",
	.pme_code = 0x00000028B0,
	.pme_short_desc = "This outer tbegin transaction cannot be dispatched until the previous tend instruction completes",
	.pme_long_desc = "This outer tbegin transaction cannot be dispatched until the previous tend instruction completes",
},
[ POWER9_PME_PM_DISP_HELD ] = {
	.pme_name = "PM_DISP_HELD",
	.pme_code = 0x0000010006,
	.pme_short_desc = "Dispatch Held",
	.pme_long_desc = "Dispatch Held",
},
[ POWER9_PME_PM_DISP_STARVED ] = {
	.pme_name = "PM_DISP_STARVED",
	.pme_code = 0x0000030008,
	.pme_short_desc = "Dispatched Starved",
	.pme_long_desc = "Dispatched Starved",
},
[ POWER9_PME_PM_DP_QP_FLOP_CMPL ] = {
	.pme_name = "PM_DP_QP_FLOP_CMPL",
	.pme_code = 0x000004D05C,
	.pme_short_desc = "Double-Precion or Quad-Precision instruction completed",
	.pme_long_desc = "Double-Precion or Quad-Precision instruction completed",
},
[ POWER9_PME_PM_DPTEG_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_DPTEG_FROM_DL2L3_MOD",
	.pme_code = 0x000004E048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_DPTEG_FROM_DL2L3_SHR",
	.pme_code = 0x000003E048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_DL4 ] = {
	.pme_name = "PM_DPTEG_FROM_DL4",
	.pme_code = 0x000003E04C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_DMEM ] = {
	.pme_name = "PM_DPTEG_FROM_DMEM",
	.pme_code = 0x000004E04C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L21_MOD ] = {
	.pme_name = "PM_DPTEG_FROM_L21_MOD",
	.pme_code = 0x000004E046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L21_SHR ] = {
	.pme_name = "PM_DPTEG_FROM_L21_SHR",
	.pme_code = 0x000003E046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L2_MEPF ] = {
	.pme_name = "PM_DPTEG_FROM_L2_MEPF",
	.pme_code = 0x000002E040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L2MISS ] = {
	.pme_name = "PM_DPTEG_FROM_L2MISS",
	.pme_code = 0x000001E04E,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_DPTEG_FROM_L2_NO_CONFLICT",
	.pme_code = 0x000001E040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L2 ] = {
	.pme_name = "PM_DPTEG_FROM_L2",
	.pme_code = 0x000001E042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_DPTEG_FROM_L31_ECO_MOD",
	.pme_code = 0x000004E044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_DPTEG_FROM_L31_ECO_SHR",
	.pme_code = 0x000003E044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L31_MOD ] = {
	.pme_name = "PM_DPTEG_FROM_L31_MOD",
	.pme_code = 0x000002E044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L31_SHR ] = {
	.pme_name = "PM_DPTEG_FROM_L31_SHR",
	.pme_code = 0x000001E046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_DPTEG_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x000003E042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L3_MEPF ] = {
	.pme_name = "PM_DPTEG_FROM_L3_MEPF",
	.pme_code = 0x000002E042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L3MISS ] = {
	.pme_name = "PM_DPTEG_FROM_L3MISS",
	.pme_code = 0x000004E04E,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_DPTEG_FROM_L3_NO_CONFLICT",
	.pme_code = 0x000001E044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_L3 ] = {
	.pme_name = "PM_DPTEG_FROM_L3",
	.pme_code = 0x000004E042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_LL4 ] = {
	.pme_name = "PM_DPTEG_FROM_LL4",
	.pme_code = 0x000001E04C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_LMEM ] = {
	.pme_name = "PM_DPTEG_FROM_LMEM",
	.pme_code = 0x000002E048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_MEMORY ] = {
	.pme_name = "PM_DPTEG_FROM_MEMORY",
	.pme_code = 0x000002E04C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_DPTEG_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x000004E04A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_DPTEG_FROM_ON_CHIP_CACHE",
	.pme_code = 0x000001E048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_DPTEG_FROM_RL2L3_MOD",
	.pme_code = 0x000002E046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_DPTEG_FROM_RL2L3_SHR",
	.pme_code = 0x000001E04A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_RL4 ] = {
	.pme_name = "PM_DPTEG_FROM_RL4",
	.pme_code = 0x000002E04A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DPTEG_FROM_RMEM ] = {
	.pme_name = "PM_DPTEG_FROM_RMEM",
	.pme_code = 0x000003E04A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_DSIDE_L2MEMACC ] = {
	.pme_name = "PM_DSIDE_L2MEMACC",
	.pme_code = 0x0000036092,
	.pme_short_desc = "Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory (excluding hpcread64 accesses), i.",
	.pme_long_desc = "Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory (excluding hpcread64 accesses), i.e., total memory accesses by RCs",
},
[ POWER9_PME_PM_DSIDE_MRU_TOUCH ] = {
	.pme_name = "PM_DSIDE_MRU_TOUCH",
	.pme_code = 0x0000026884,
	.pme_short_desc = "D-side L2 MRU touch sent to L2",
	.pme_long_desc = "D-side L2 MRU touch sent to L2",
},
[ POWER9_PME_PM_DSIDE_OTHER_64B_L2MEMACC ] = {
	.pme_name = "PM_DSIDE_OTHER_64B_L2MEMACC",
	.pme_code = 0x0000036892,
	.pme_short_desc = "Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory that was for hpc_read64, (RC had to fetch other 64B of a line from MC) i.",
	.pme_long_desc = "Valid when first beat of data comes in for an D-side fetch where data came EXCLUSIVELY from memory that was for hpc_read64, (RC had to fetch other 64B of a line from MC) i.e., number of times RC had to go to memory to get 'missing' 64B",
},
[ POWER9_PME_PM_DSLB_MISS ] = {
	.pme_name = "PM_DSLB_MISS",
	.pme_code = 0x000000D0A8,
	.pme_short_desc = "Data SLB Miss - Total of all segment sizes",
	.pme_long_desc = "Data SLB Miss - Total of all segment sizes",
},
[ POWER9_PME_PM_DSLB_MISS_ALT ] = {
	.pme_name = "PM_DSLB_MISS_ALT",
	.pme_code = 0x0000010016,
	.pme_short_desc = "gate_and(sd_pc_c0_comp_valid AND sd_pc_c0_comp_thread(0:1)=tid,sd_pc_c0_comp_ppc_count(0:3)) + gate_and(sd_pc_c1_comp_valid AND sd_pc_c1_comp_thread(0:1)=tid,sd_pc_c1_comp_ppc_count(0:3))",
	.pme_long_desc = "gate_and(sd_pc_c0_comp_valid AND sd_pc_c0_comp_thread(0:1)=tid,sd_pc_c0_comp_ppc_count(0:3)) + gate_and(sd_pc_c1_comp_valid AND sd_pc_c1_comp_thread(0:1)=tid,sd_pc_c1_comp_ppc_count(0:3))",
},
[ POWER9_PME_PM_DTLB_MISS_16G ] = {
	.pme_name = "PM_DTLB_MISS_16G",
	.pme_code = 0x000001C058,
	.pme_short_desc = "Data TLB Miss page size 16G",
	.pme_long_desc = "Data TLB Miss page size 16G",
},
[ POWER9_PME_PM_DTLB_MISS_16M ] = {
	.pme_name = "PM_DTLB_MISS_16M",
	.pme_code = 0x000004C056,
	.pme_short_desc = "Data TLB Miss page size 16M",
	.pme_long_desc = "Data TLB Miss page size 16M",
},
[ POWER9_PME_PM_DTLB_MISS_1G ] = {
	.pme_name = "PM_DTLB_MISS_1G",
	.pme_code = 0x000004C05A,
	.pme_short_desc = "Data TLB reload (after a miss) page size 1G.",
	.pme_long_desc = "Data TLB reload (after a miss) page size 1G. Implies radix translation was used",
},
[ POWER9_PME_PM_DTLB_MISS_2M ] = {
	.pme_name = "PM_DTLB_MISS_2M",
	.pme_code = 0x000001C05C,
	.pme_short_desc = "Data TLB reload (after a miss) page size 2M.",
	.pme_long_desc = "Data TLB reload (after a miss) page size 2M. Implies radix translation was used",
},
[ POWER9_PME_PM_DTLB_MISS_4K ] = {
	.pme_name = "PM_DTLB_MISS_4K",
	.pme_code = 0x000002C056,
	.pme_short_desc = "Data TLB Miss page size 4k",
	.pme_long_desc = "Data TLB Miss page size 4k",
},
[ POWER9_PME_PM_DTLB_MISS_64K ] = {
	.pme_name = "PM_DTLB_MISS_64K",
	.pme_code = 0x000003C056,
	.pme_short_desc = "Data TLB Miss page size 64K",
	.pme_long_desc = "Data TLB Miss page size 64K",
},
[ POWER9_PME_PM_DTLB_MISS ] = {
	.pme_name = "PM_DTLB_MISS",
	.pme_code = 0x00000300FC,
	.pme_short_desc = "Data PTEG reload",
	.pme_long_desc = "Data PTEG reload",
},
[ POWER9_PME_PM_SPACEHOLDER_0000040062 ] = {
	.pme_name = "PM_SPACEHOLDER_0000040062",
	.pme_code = 0x0000040062,
	.pme_short_desc = "SPACE_HOLDER for event 0000040062",
	.pme_long_desc = "SPACE_HOLDER for event 0000040062",
},
[ POWER9_PME_PM_SPACEHOLDER_0000040064 ] = {
	.pme_name = "PM_SPACEHOLDER_0000040064",
	.pme_code = 0x0000040064,
	.pme_short_desc = "SPACE_HOLDER for event 0000040064",
	.pme_long_desc = "SPACE_HOLDER for event 0000040064",
},
[ POWER9_PME_PM_EAT_FORCE_MISPRED ] = {
	.pme_name = "PM_EAT_FORCE_MISPRED",
	.pme_code = 0x00000050A8,
	.pme_short_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT.",
	.pme_long_desc = "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued",
},
[ POWER9_PME_PM_EAT_FULL_CYC ] = {
	.pme_name = "PM_EAT_FULL_CYC",
	.pme_code = 0x0000004084,
	.pme_short_desc = "Cycles No room in EAT",
	.pme_long_desc = "Cycles No room in EAT",
},
[ POWER9_PME_PM_EE_OFF_EXT_INT ] = {
	.pme_name = "PM_EE_OFF_EXT_INT",
	.pme_code = 0x0000002080,
	.pme_short_desc = "CyclesMSR[EE] is off and external interrupts are active",
	.pme_long_desc = "CyclesMSR[EE] is off and external interrupts are active",
},
[ POWER9_PME_PM_EXT_INT ] = {
	.pme_name = "PM_EXT_INT",
	.pme_code = 0x00000200F8,
	.pme_short_desc = "external interrupt",
	.pme_long_desc = "external interrupt",
},
[ POWER9_PME_PM_FLOP_CMPL ] = {
	.pme_name = "PM_FLOP_CMPL",
	.pme_code = 0x000004505E,
	.pme_short_desc = "Floating Point Operation Finished",
	.pme_long_desc = "Floating Point Operation Finished",
},
[ POWER9_PME_PM_FLUSH_COMPLETION ] = {
	.pme_name = "PM_FLUSH_COMPLETION",
	.pme_code = 0x0000030012,
	.pme_short_desc = "The instruction that was next to complete did not complete because it suffered a flush",
	.pme_long_desc = "The instruction that was next to complete did not complete because it suffered a flush",
},
[ POWER9_PME_PM_FLUSH_DISP_SB ] = {
	.pme_name = "PM_FLUSH_DISP_SB",
	.pme_code = 0x0000002088,
	.pme_short_desc = "Dispatch Flush: Scoreboard",
	.pme_long_desc = "Dispatch Flush: Scoreboard",
},
[ POWER9_PME_PM_FLUSH_DISP_TLBIE ] = {
	.pme_name = "PM_FLUSH_DISP_TLBIE",
	.pme_code = 0x0000002888,
	.pme_short_desc = "Dispatch Flush: TLBIE",
	.pme_long_desc = "Dispatch Flush: TLBIE",
},
[ POWER9_PME_PM_FLUSH_DISP ] = {
	.pme_name = "PM_FLUSH_DISP",
	.pme_code = 0x0000002880,
	.pme_short_desc = "Dispatch flush",
	.pme_long_desc = "Dispatch flush",
},
[ POWER9_PME_PM_FLUSH_HB_RESTORE_CYC ] = {
	.pme_name = "PM_FLUSH_HB_RESTORE_CYC",
	.pme_code = 0x0000002084,
	.pme_short_desc = "Cycles in which no new instructions can be dispatched to the ICT after a flush.",
	.pme_long_desc = "Cycles in which no new instructions can be dispatched to the ICT after a flush. History buffer recovery",
},
[ POWER9_PME_PM_FLUSH_LSU ] = {
	.pme_name = "PM_FLUSH_LSU",
	.pme_code = 0x00000058A4,
	.pme_short_desc = "LSU flushes.",
	.pme_long_desc = "LSU flushes. Includes all lsu flushes",
},
[ POWER9_PME_PM_FLUSH_MPRED ] = {
	.pme_name = "PM_FLUSH_MPRED",
	.pme_code = 0x00000050A4,
	.pme_short_desc = "Branch mispredict flushes.",
	.pme_long_desc = "Branch mispredict flushes. Includes target and address misprecition",
},
[ POWER9_PME_PM_FLUSH ] = {
	.pme_name = "PM_FLUSH",
	.pme_code = 0x00000400F8,
	.pme_short_desc = "Flush (any type)",
	.pme_long_desc = "Flush (any type)",
},
[ POWER9_PME_PM_FMA_CMPL ] = {
	.pme_name = "PM_FMA_CMPL",
	.pme_code = 0x0000045054,
	.pme_short_desc = "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only.",
	.pme_long_desc = "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only. ",
},
[ POWER9_PME_PM_FORCED_NOP ] = {
	.pme_name = "PM_FORCED_NOP",
	.pme_code = 0x000000509C,
	.pme_short_desc = "Instruction was forced to execute as a nop because it was found to behave like a nop (have no effect) at decode time",
	.pme_long_desc = "Instruction was forced to execute as a nop because it was found to behave like a nop (have no effect) at decode time",
},
[ POWER9_PME_PM_FREQ_DOWN ] = {
	.pme_name = "PM_FREQ_DOWN",
	.pme_code = 0x000003000C,
	.pme_short_desc = "Power Management: Below Threshold B",
	.pme_long_desc = "Power Management: Below Threshold B",
},
[ POWER9_PME_PM_FREQ_UP ] = {
	.pme_name = "PM_FREQ_UP",
	.pme_code = 0x000004000C,
	.pme_short_desc = "Power Management: Above Threshold A",
	.pme_long_desc = "Power Management: Above Threshold A",
},
[ POWER9_PME_PM_FXU_1PLUS_BUSY ] = {
	.pme_name = "PM_FXU_1PLUS_BUSY",
	.pme_code = 0x000003000E,
	.pme_short_desc = "At least one of the 4 FXU units is busy",
	.pme_long_desc = "At least one of the 4 FXU units is busy",
},
[ POWER9_PME_PM_FXU_BUSY ] = {
	.pme_name = "PM_FXU_BUSY",
	.pme_code = 0x000002000E,
	.pme_short_desc = "Cycles in which all 4 FXUs are busy.",
	.pme_long_desc = "Cycles in which all 4 FXUs are busy. The FXU is running at capacity",
},
[ POWER9_PME_PM_FXU_FIN ] = {
	.pme_name = "PM_FXU_FIN",
	.pme_code = 0x0000040004,
	.pme_short_desc = "The fixed point unit Unit finished an instruction.",
	.pme_long_desc = "The fixed point unit Unit finished an instruction. Instructions that finish may not necessary complete.",
},
[ POWER9_PME_PM_FXU_IDLE ] = {
	.pme_name = "PM_FXU_IDLE",
	.pme_code = 0x0000024052,
	.pme_short_desc = "Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle",
	.pme_long_desc = "Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle",
},
[ POWER9_PME_PM_GRP_PUMP_CPRED ] = {
	.pme_name = "PM_GRP_PUMP_CPRED",
	.pme_code = 0x0000020050,
	.pme_short_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER9_PME_PM_GRP_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_GRP_PUMP_MPRED_RTY",
	.pme_code = 0x0000010052,
	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER9_PME_PM_GRP_PUMP_MPRED ] = {
	.pme_name = "PM_GRP_PUMP_MPRED",
	.pme_code = 0x0000020052,
	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER9_PME_PM_HV_CYC ] = {
	.pme_name = "PM_HV_CYC",
	.pme_code = 0x000002000A,
	.pme_short_desc = "Cycles in which msr_hv is high.",
	.pme_long_desc = "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration",
},
[ POWER9_PME_PM_HWSYNC ] = {
	.pme_name = "PM_HWSYNC",
	.pme_code = 0x00000050A0,
	.pme_short_desc = "Hwsync instruction decoded and transferred",
	.pme_long_desc = "Hwsync instruction decoded and transferred",
},
[ POWER9_PME_PM_IBUF_FULL_CYC ] = {
	.pme_name = "PM_IBUF_FULL_CYC",
	.pme_code = 0x0000004884,
	.pme_short_desc = "Cycles No room in ibuff",
	.pme_long_desc = "Cycles No room in ibuff",
},
[ POWER9_PME_PM_IC_DEMAND_CYC ] = {
	.pme_name = "PM_IC_DEMAND_CYC",
	.pme_code = 0x0000010018,
	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
	.pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
},
[ POWER9_PME_PM_IC_DEMAND_L2_BHT_REDIRECT ] = {
	.pme_name = "PM_IC_DEMAND_L2_BHT_REDIRECT",
	.pme_code = 0x0000004098,
	.pme_short_desc = "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)",
	.pme_long_desc = "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles)",
},
[ POWER9_PME_PM_IC_DEMAND_L2_BR_REDIRECT ] = {
	.pme_name = "PM_IC_DEMAND_L2_BR_REDIRECT",
	.pme_code = 0x0000004898,
	.pme_short_desc = "L2 I cache demand request due to branch Mispredict ( 15 cycle path)",
	.pme_long_desc = "L2 I cache demand request due to branch Mispredict ( 15 cycle path)",
},
[ POWER9_PME_PM_IC_DEMAND_REQ ] = {
	.pme_name = "PM_IC_DEMAND_REQ",
	.pme_code = 0x0000004088,
	.pme_short_desc = "Demand Instruction fetch request",
	.pme_long_desc = "Demand Instruction fetch request",
},
[ POWER9_PME_PM_IC_INVALIDATE ] = {
	.pme_name = "PM_IC_INVALIDATE",
	.pme_code = 0x0000005888,
	.pme_short_desc = "Ic line invalidated",
	.pme_long_desc = "Ic line invalidated",
},
[ POWER9_PME_PM_IC_MISS_CMPL ] = {
	.pme_name = "PM_IC_MISS_CMPL",
	.pme_code = 0x0000045058,
	.pme_short_desc = "Non-speculative icache miss, counted at completion",
	.pme_long_desc = "Non-speculative icache miss, counted at completion",
},
[ POWER9_PME_PM_IC_MISS_ICBI ] = {
	.pme_name = "PM_IC_MISS_ICBI",
	.pme_code = 0x0000005094,
	.pme_short_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on.",
	.pme_long_desc = "threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out",
},
[ POWER9_PME_PM_IC_PREF_CANCEL_HIT ] = {
	.pme_name = "PM_IC_PREF_CANCEL_HIT",
	.pme_code = 0x0000004890,
	.pme_short_desc = "Prefetch Canceled due to icache hit",
	.pme_long_desc = "Prefetch Canceled due to icache hit",
},
[ POWER9_PME_PM_IC_PREF_CANCEL_L2 ] = {
	.pme_name = "PM_IC_PREF_CANCEL_L2",
	.pme_code = 0x0000004094,
	.pme_short_desc = "L2 Squashed a demand or prefetch request",
	.pme_long_desc = "L2 Squashed a demand or prefetch request",
},
[ POWER9_PME_PM_IC_PREF_CANCEL_PAGE ] = {
	.pme_name = "PM_IC_PREF_CANCEL_PAGE",
	.pme_code = 0x0000004090,
	.pme_short_desc = "Prefetch Canceled due to page boundary",
	.pme_long_desc = "Prefetch Canceled due to page boundary",
},
[ POWER9_PME_PM_IC_PREF_REQ ] = {
	.pme_name = "PM_IC_PREF_REQ",
	.pme_code = 0x0000004888,
	.pme_short_desc = "Instruction prefetch requests",
	.pme_long_desc = "Instruction prefetch requests",
},
[ POWER9_PME_PM_IC_PREF_WRITE ] = {
	.pme_name = "PM_IC_PREF_WRITE",
	.pme_code = 0x000000488C,
	.pme_short_desc = "Instruction prefetch written into IL1",
	.pme_long_desc = "Instruction prefetch written into IL1",
},
[ POWER9_PME_PM_IC_RELOAD_PRIVATE ] = {
	.pme_name = "PM_IC_RELOAD_PRIVATE",
	.pme_code = 0x0000004894,
	.pme_short_desc = "Reloading line was brought in private for a specific thread.",
	.pme_long_desc = "Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight threads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was invalidat",
},
[ POWER9_PME_PM_ICT_EMPTY_CYC ] = {
	.pme_name = "PM_ICT_EMPTY_CYC",
	.pme_code = 0x0000020008,
	.pme_short_desc = "Cycles in which the ICT is completely empty.",
	.pme_long_desc = "Cycles in which the ICT is completely empty. No itags are assigned to any thread",
},
[ POWER9_PME_PM_ICT_NOSLOT_BR_MPRED_ICMISS ] = {
	.pme_name = "PM_ICT_NOSLOT_BR_MPRED_ICMISS",
	.pme_code = 0x0000034058,
	.pme_short_desc = "Ict empty for this thread due to Icache Miss and branch mispred",
	.pme_long_desc = "Ict empty for this thread due to Icache Miss and branch mispred",
},
[ POWER9_PME_PM_ICT_NOSLOT_BR_MPRED ] = {
	.pme_name = "PM_ICT_NOSLOT_BR_MPRED",
	.pme_code = 0x000004D01E,
	.pme_short_desc = "Ict empty for this thread due to branch mispred",
	.pme_long_desc = "Ict empty for this thread due to branch mispred",
},
[ POWER9_PME_PM_ICT_NOSLOT_CYC ] = {
	.pme_name = "PM_ICT_NOSLOT_CYC",
	.pme_code = 0x00000100F8,
	.pme_short_desc = "Number of cycles the ICT has no itags assigned to this thread",
	.pme_long_desc = "Number of cycles the ICT has no itags assigned to this thread",
},
[ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_HB_FULL ] = {
	.pme_name = "PM_ICT_NOSLOT_DISP_HELD_HB_FULL",
	.pme_code = 0x0000030018,
	.pme_short_desc = "Ict empty for this thread due to dispatch holds because the History Buffer was full.",
	.pme_long_desc = "Ict empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)",
},
[ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_ISSQ ] = {
	.pme_name = "PM_ICT_NOSLOT_DISP_HELD_ISSQ",
	.pme_code = 0x000002D01E,
	.pme_short_desc = "Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full",
	.pme_long_desc = "Ict empty for this thread due to dispatch hold on this thread due to Issue q full, BRQ full, XVCF Full, Count cache, Link, Tar full",
},
[ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_SYNC ] = {
	.pme_name = "PM_ICT_NOSLOT_DISP_HELD_SYNC",
	.pme_code = 0x000004D01C,
	.pme_short_desc = "Dispatch held due to a synchronizing instruction at dispatch",
	.pme_long_desc = "Dispatch held due to a synchronizing instruction at dispatch",
},
[ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD_TBEGIN ] = {
	.pme_name = "PM_ICT_NOSLOT_DISP_HELD_TBEGIN",
	.pme_code = 0x0000010064,
	.pme_short_desc = "the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch",
	.pme_long_desc = "the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch",
},
[ POWER9_PME_PM_ICT_NOSLOT_DISP_HELD ] = {
	.pme_name = "PM_ICT_NOSLOT_DISP_HELD",
	.pme_code = 0x000004E01A,
	.pme_short_desc = "Cycles in which the NTC instruction is held at dispatch for any reason",
	.pme_long_desc = "Cycles in which the NTC instruction is held at dispatch for any reason",
},
[ POWER9_PME_PM_ICT_NOSLOT_IC_L3MISS ] = {
	.pme_name = "PM_ICT_NOSLOT_IC_L3MISS",
	.pme_code = 0x000004E010,
	.pme_short_desc = "Ict empty for this thread due to icache misses that were sourced from beyond the local L3.",
	.pme_long_desc = "Ict empty for this thread due to icache misses that were sourced from beyond the local L3. The source could be local/remote/distant memory or another core's cache",
},
[ POWER9_PME_PM_ICT_NOSLOT_IC_L3 ] = {
	.pme_name = "PM_ICT_NOSLOT_IC_L3",
	.pme_code = 0x000003E052,
	.pme_short_desc = "Ict empty for this thread due to icache misses that were sourced from the local L3",
	.pme_long_desc = "Ict empty for this thread due to icache misses that were sourced from the local L3",
},
[ POWER9_PME_PM_ICT_NOSLOT_IC_MISS ] = {
	.pme_name = "PM_ICT_NOSLOT_IC_MISS",
	.pme_code = 0x000002D01A,
	.pme_short_desc = "Ict empty for this thread due to Icache Miss",
	.pme_long_desc = "Ict empty for this thread due to Icache Miss",
},
[ POWER9_PME_PM_IERAT_RELOAD_16M ] = {
	.pme_name = "PM_IERAT_RELOAD_16M",
	.pme_code = 0x000004006A,
	.pme_short_desc = "IERAT Reloaded (Miss) for a 16M page",
	.pme_long_desc = "IERAT Reloaded (Miss) for a 16M page",
},
[ POWER9_PME_PM_IERAT_RELOAD_4K ] = {
	.pme_name = "PM_IERAT_RELOAD_4K",
	.pme_code = 0x0000020064,
	.pme_short_desc = "IERAT reloaded (after a miss) for 4K pages",
	.pme_long_desc = "IERAT reloaded (after a miss) for 4K pages",
},
[ POWER9_PME_PM_IERAT_RELOAD_64K ] = {
	.pme_name = "PM_IERAT_RELOAD_64K",
	.pme_code = 0x000003006A,
	.pme_short_desc = "IERAT Reloaded (Miss) for a 64k page",
	.pme_long_desc = "IERAT Reloaded (Miss) for a 64k page",
},
[ POWER9_PME_PM_IERAT_RELOAD ] = {
	.pme_name = "PM_IERAT_RELOAD",
	.pme_code = 0x00000100F6,
	.pme_short_desc = "Number of I-ERAT reloads",
	.pme_long_desc = "Number of I-ERAT reloads",
},
[ POWER9_PME_PM_IFETCH_THROTTLE ] = {
	.pme_name = "PM_IFETCH_THROTTLE",
	.pme_code = 0x000003405E,
	.pme_short_desc = "Cycles in which Instruction fetch throttle was active.",
	.pme_long_desc = "Cycles in which Instruction fetch throttle was active.",
},
[ POWER9_PME_PM_INST_CHIP_PUMP_CPRED ] = {
	.pme_name = "PM_INST_CHIP_PUMP_CPRED",
	.pme_code = 0x0000014050,
	.pme_short_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
	.pme_long_desc = "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
},
/* See also alternate entries for 0000010002 / POWER9_PME_PM_INST_CMPL with code(s) 0000020002 0000030002 0000040002 at the bottom of this table. \n */
[ POWER9_PME_PM_INST_CMPL ] = {
	.pme_name = "PM_INST_CMPL",
	.pme_code = 0x0000010002,
	.pme_short_desc = "Number of PowerPC Instructions that completed.",
	.pme_long_desc = "Number of PowerPC Instructions that completed.",
},
/* See also alternate entries for 00000200F2 / POWER9_PME_PM_INST_DISP with code(s) 00000300F2 at the bottom of this table. \n */
[ POWER9_PME_PM_INST_DISP ] = {
	.pme_name = "PM_INST_DISP",
	.pme_code = 0x00000200F2,
	.pme_short_desc = "# PPC Dispatched",
	.pme_long_desc = "# PPC Dispatched",
},
[ POWER9_PME_PM_INST_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_INST_FROM_DL2L3_MOD",
	.pme_code = 0x0000044048,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_INST_FROM_DL2L3_SHR",
	.pme_code = 0x0000034048,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_DL4 ] = {
	.pme_name = "PM_INST_FROM_DL4",
	.pme_code = 0x000003404C,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_DMEM ] = {
	.pme_name = "PM_INST_FROM_DMEM",
	.pme_code = 0x000004404C,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L1 ] = {
	.pme_name = "PM_INST_FROM_L1",
	.pme_code = 0x0000004080,
	.pme_short_desc = "Instruction fetches from L1.",
	.pme_long_desc = "Instruction fetches from L1. L1 instruction hit",
},
[ POWER9_PME_PM_INST_FROM_L21_MOD ] = {
	.pme_name = "PM_INST_FROM_L21_MOD",
	.pme_code = 0x0000044046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L21_SHR ] = {
	.pme_name = "PM_INST_FROM_L21_SHR",
	.pme_code = 0x0000034046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x0000034040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_INST_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x0000044040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L2_MEPF ] = {
	.pme_name = "PM_INST_FROM_L2_MEPF",
	.pme_code = 0x0000024040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state.",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L2MISS ] = {
	.pme_name = "PM_INST_FROM_L2MISS",
	.pme_code = 0x000001404E,
	.pme_short_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_INST_FROM_L2_NO_CONFLICT",
	.pme_code = 0x0000014040,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L2 ] = {
	.pme_name = "PM_INST_FROM_L2",
	.pme_code = 0x0000014042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_INST_FROM_L31_ECO_MOD",
	.pme_code = 0x0000044044,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_INST_FROM_L31_ECO_SHR",
	.pme_code = 0x0000034044,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L31_MOD ] = {
	.pme_name = "PM_INST_FROM_L31_MOD",
	.pme_code = 0x0000024044,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L31_SHR ] = {
	.pme_name = "PM_INST_FROM_L31_SHR",
	.pme_code = 0x0000014046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_INST_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x0000034042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L3_MEPF ] = {
	.pme_name = "PM_INST_FROM_L3_MEPF",
	.pme_code = 0x0000024042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state.",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L3MISS_MOD ] = {
	.pme_name = "PM_INST_FROM_L3MISS_MOD",
	.pme_code = 0x000004404E,
	.pme_short_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch",
	.pme_long_desc = "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch",
},
[ POWER9_PME_PM_INST_FROM_L3MISS ] = {
	.pme_name = "PM_INST_FROM_L3MISS",
	.pme_code = 0x00000300FA,
	.pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet",
	.pme_long_desc = "Marked instruction was reloaded from a location beyond the local chiplet",
},
[ POWER9_PME_PM_INST_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_INST_FROM_L3_NO_CONFLICT",
	.pme_code = 0x0000014044,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_L3 ] = {
	.pme_name = "PM_INST_FROM_L3",
	.pme_code = 0x0000044042,
	.pme_short_desc = "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_LL4 ] = {
	.pme_name = "PM_INST_FROM_LL4",
	.pme_code = 0x000001404C,
	.pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_LMEM ] = {
	.pme_name = "PM_INST_FROM_LMEM",
	.pme_code = 0x0000024048,
	.pme_short_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_MEMORY ] = {
	.pme_name = "PM_INST_FROM_MEMORY",
	.pme_code = 0x000002404C,
	.pme_short_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_INST_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x000004404A,
	.pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_INST_FROM_ON_CHIP_CACHE",
	.pme_code = 0x0000014048,
	.pme_short_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_INST_FROM_RL2L3_MOD",
	.pme_code = 0x0000024046,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_INST_FROM_RL2L3_SHR",
	.pme_code = 0x000001404A,
	.pme_short_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_RL4 ] = {
	.pme_name = "PM_INST_FROM_RL4",
	.pme_code = 0x000002404A,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_FROM_RMEM ] = {
	.pme_name = "PM_INST_FROM_RMEM",
	.pme_code = 0x000003404A,
	.pme_short_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
	.pme_long_desc = "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
},
[ POWER9_PME_PM_INST_GRP_PUMP_CPRED ] = {
	.pme_name = "PM_INST_GRP_PUMP_CPRED",
	.pme_code = 0x000002C05C,
	.pme_short_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)",
	.pme_long_desc = "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)",
},
[ POWER9_PME_PM_INST_GRP_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_INST_GRP_PUMP_MPRED_RTY",
	.pme_code = 0x0000014052,
	.pme_short_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch",
	.pme_long_desc = "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch",
},
[ POWER9_PME_PM_INST_GRP_PUMP_MPRED ] = {
	.pme_name = "PM_INST_GRP_PUMP_MPRED",
	.pme_code = 0x000002C05E,
	.pme_short_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only)",
	.pme_long_desc = "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for an instruction fetch (demand only)",
},
[ POWER9_PME_PM_INST_IMC_MATCH_CMPL ] = {
	.pme_name = "PM_INST_IMC_MATCH_CMPL",
	.pme_code = 0x000004001C,
	.pme_short_desc = "IMC Match Count",
	.pme_long_desc = "IMC Match Count",
},
[ POWER9_PME_PM_INST_PUMP_CPRED ] = {
	.pme_name = "PM_INST_PUMP_CPRED",
	.pme_code = 0x0000014054,
	.pme_short_desc = "Pump prediction correct.",
	.pme_long_desc = "Pump prediction correct. Counts across all types of pumps for an instruction fetch",
},
[ POWER9_PME_PM_INST_PUMP_MPRED ] = {
	.pme_name = "PM_INST_PUMP_MPRED",
	.pme_code = 0x0000044052,
	.pme_short_desc = "Pump misprediction.",
	.pme_long_desc = "Pump misprediction. Counts across all types of pumps for an instruction fetch",
},
[ POWER9_PME_PM_INST_SYS_PUMP_CPRED ] = {
	.pme_name = "PM_INST_SYS_PUMP_CPRED",
	.pme_code = 0x0000034050,
	.pme_short_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch",
	.pme_long_desc = "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch",
},
[ POWER9_PME_PM_INST_SYS_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_INST_SYS_PUMP_MPRED_RTY",
	.pme_code = 0x0000044050,
	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch",
	.pme_long_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch",
},
[ POWER9_PME_PM_INST_SYS_PUMP_MPRED ] = {
	.pme_name = "PM_INST_SYS_PUMP_MPRED",
	.pme_code = 0x0000034052,
	.pme_short_desc = "Final Pump Scope (system) mispredicted.",
	.pme_long_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch",
},
[ POWER9_PME_PM_IOPS_CMPL ] = {
	.pme_name = "PM_IOPS_CMPL",
	.pme_code = 0x0000024050,
	.pme_short_desc = "Internal Operations completed",
	.pme_long_desc = "Internal Operations completed",
},
[ POWER9_PME_PM_IPTEG_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_IPTEG_FROM_DL2L3_MOD",
	.pme_code = 0x0000045048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_IPTEG_FROM_DL2L3_SHR",
	.pme_code = 0x0000035048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_DL4 ] = {
	.pme_name = "PM_IPTEG_FROM_DL4",
	.pme_code = 0x000003504C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_DMEM ] = {
	.pme_name = "PM_IPTEG_FROM_DMEM",
	.pme_code = 0x000004504C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L21_MOD ] = {
	.pme_name = "PM_IPTEG_FROM_L21_MOD",
	.pme_code = 0x0000045046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L21_SHR ] = {
	.pme_name = "PM_IPTEG_FROM_L21_SHR",
	.pme_code = 0x0000035046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L2_MEPF ] = {
	.pme_name = "PM_IPTEG_FROM_L2_MEPF",
	.pme_code = 0x0000025040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L2MISS ] = {
	.pme_name = "PM_IPTEG_FROM_L2MISS",
	.pme_code = 0x000001504E,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_IPTEG_FROM_L2_NO_CONFLICT",
	.pme_code = 0x0000015040,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L2 ] = {
	.pme_name = "PM_IPTEG_FROM_L2",
	.pme_code = 0x0000015042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_IPTEG_FROM_L31_ECO_MOD",
	.pme_code = 0x0000045044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_IPTEG_FROM_L31_ECO_SHR",
	.pme_code = 0x0000035044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L31_MOD ] = {
	.pme_name = "PM_IPTEG_FROM_L31_MOD",
	.pme_code = 0x0000025044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L31_SHR ] = {
	.pme_name = "PM_IPTEG_FROM_L31_SHR",
	.pme_code = 0x0000015046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_IPTEG_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x0000035042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L3_MEPF ] = {
	.pme_name = "PM_IPTEG_FROM_L3_MEPF",
	.pme_code = 0x0000025042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L3MISS ] = {
	.pme_name = "PM_IPTEG_FROM_L3MISS",
	.pme_code = 0x000004504E,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_IPTEG_FROM_L3_NO_CONFLICT",
	.pme_code = 0x0000015044,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_L3 ] = {
	.pme_name = "PM_IPTEG_FROM_L3",
	.pme_code = 0x0000045042,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_LL4 ] = {
	.pme_name = "PM_IPTEG_FROM_LL4",
	.pme_code = 0x000001504C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_LMEM ] = {
	.pme_name = "PM_IPTEG_FROM_LMEM",
	.pme_code = 0x0000025048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_MEMORY ] = {
	.pme_name = "PM_IPTEG_FROM_MEMORY",
	.pme_code = 0x000002504C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_IPTEG_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x000004504A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_IPTEG_FROM_ON_CHIP_CACHE",
	.pme_code = 0x0000015048,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_IPTEG_FROM_RL2L3_MOD",
	.pme_code = 0x0000025046,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_IPTEG_FROM_RL2L3_SHR",
	.pme_code = 0x000001504A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_RL4 ] = {
	.pme_name = "PM_IPTEG_FROM_RL4",
	.pme_code = 0x000002504A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request",
},
[ POWER9_PME_PM_IPTEG_FROM_RMEM ] = {
	.pme_name = "PM_IPTEG_FROM_RMEM",
	.pme_code = 0x000003504A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request",
},
[ POWER9_PME_PM_ISIDE_DISP_FAIL_ADDR ] = {
	.pme_name = "PM_ISIDE_DISP_FAIL_ADDR",
	.pme_code = 0x000002608A,
	.pme_short_desc = "All I-side dispatch attempts for this thread that failed due to a addr collision with another machine (excludes i_l2mru_tch_reqs)",
	.pme_long_desc = "All I-side dispatch attempts for this thread that failed due to a addr collision with another machine (excludes i_l2mru_tch_reqs)",
},
[ POWER9_PME_PM_ISIDE_DISP_FAIL_OTHER ] = {
	.pme_name = "PM_ISIDE_DISP_FAIL_OTHER",
	.pme_code = 0x000002688A,
	.pme_short_desc = "All I-side dispatch attempts for this thread that failed due to a reason other than addrs collision (excludes i_l2mru_tch_reqs)",
	.pme_long_desc = "All I-side dispatch attempts for this thread that failed due to a reason other than addrs collision (excludes i_l2mru_tch_reqs)",
},
[ POWER9_PME_PM_ISIDE_DISP ] = {
	.pme_name = "PM_ISIDE_DISP",
	.pme_code = 0x000001688A,
	.pme_short_desc = "All I-side dispatch attempts for this thread (excludes i_l2mru_tch_reqs)",
	.pme_long_desc = "All I-side dispatch attempts for this thread (excludes i_l2mru_tch_reqs)",
},
[ POWER9_PME_PM_ISIDE_L2MEMACC ] = {
	.pme_name = "PM_ISIDE_L2MEMACC",
	.pme_code = 0x0000026890,
	.pme_short_desc = "Valid when first beat of data comes in for an I-side fetch where data came from memory",
	.pme_long_desc = "Valid when first beat of data comes in for an I-side fetch where data came from memory",
},
[ POWER9_PME_PM_ISIDE_MRU_TOUCH ] = {
	.pme_name = "PM_ISIDE_MRU_TOUCH",
	.pme_code = 0x0000046880,
	.pme_short_desc = "I-side L2 MRU touch sent to L2 for this thread",
	.pme_long_desc = "I-side L2 MRU touch sent to L2 for this thread",
},
[ POWER9_PME_PM_ISLB_MISS ] = {
	.pme_name = "PM_ISLB_MISS",
	.pme_code = 0x000000D8A8,
	.pme_short_desc = "Instruction SLB Miss - Total of all segment sizes",
	.pme_long_desc = "Instruction SLB Miss - Total of all segment sizes",
},
[ POWER9_PME_PM_ISLB_MISS_ALT ] = {
	.pme_name = "PM_ISLB_MISS_ALT",
	.pme_code = 0x0000040006,
	.pme_short_desc = "Number of ISLB misses for this thread",
	.pme_long_desc = "Number of ISLB misses for this thread",
},
[ POWER9_PME_PM_ISQ_0_8_ENTRIES ] = {
	.pme_name = "PM_ISQ_0_8_ENTRIES",
	.pme_code = 0x000003005A,
	.pme_short_desc = "Cycles in which 8 or less Issue Queue entries are in use.",
	.pme_long_desc = "Cycles in which 8 or less Issue Queue entries are in use. This is a shared event, not per thread",
},
[ POWER9_PME_PM_ISQ_36_44_ENTRIES ] = {
	.pme_name = "PM_ISQ_36_44_ENTRIES",
	.pme_code = 0x000004000A,
	.pme_short_desc = "Cycles in which 36 or more Issue Queue entries are in use.",
	.pme_long_desc = "Cycles in which 36 or more Issue Queue entries are in use. This is a shared event, not per thread. There are 44 issue queue entries across 4 slices in the whole core",
},
[ POWER9_PME_PM_ISU0_ISS_HOLD_ALL ] = {
	.pme_name = "PM_ISU0_ISS_HOLD_ALL",
	.pme_code = 0x0000003080,
	.pme_short_desc = "All ISU rejects",
	.pme_long_desc = "All ISU rejects",
},
[ POWER9_PME_PM_ISU1_ISS_HOLD_ALL ] = {
	.pme_name = "PM_ISU1_ISS_HOLD_ALL",
	.pme_code = 0x0000003084,
	.pme_short_desc = "All ISU rejects",
	.pme_long_desc = "All ISU rejects",
},
[ POWER9_PME_PM_ISU2_ISS_HOLD_ALL ] = {
	.pme_name = "PM_ISU2_ISS_HOLD_ALL",
	.pme_code = 0x0000003880,
	.pme_short_desc = "All ISU rejects",
	.pme_long_desc = "All ISU rejects",
},
[ POWER9_PME_PM_ISU3_ISS_HOLD_ALL ] = {
	.pme_name = "PM_ISU3_ISS_HOLD_ALL",
	.pme_code = 0x0000003884,
	.pme_short_desc = "All ISU rejects",
	.pme_long_desc = "All ISU rejects",
},
[ POWER9_PME_PM_ISYNC ] = {
	.pme_name = "PM_ISYNC",
	.pme_code = 0x0000002884,
	.pme_short_desc = "Isync completion count per thread",
	.pme_long_desc = "Isync completion count per thread",
},
[ POWER9_PME_PM_ITLB_MISS ] = {
	.pme_name = "PM_ITLB_MISS",
	.pme_code = 0x00000400FC,
	.pme_short_desc = "ITLB Reloaded.",
	.pme_long_desc = "ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed",
},
[ POWER9_PME_PM_L1_DCACHE_RELOADED_ALL ] = {
	.pme_name = "PM_L1_DCACHE_RELOADED_ALL",
	.pme_code = 0x000001002C,
	.pme_short_desc = "L1 data cache reloaded for demand.",
	.pme_long_desc = "L1 data cache reloaded for demand. If MMCR1[16] is 1, prefetches will be included as well",
},
[ POWER9_PME_PM_L1_DCACHE_RELOAD_VALID ] = {
	.pme_name = "PM_L1_DCACHE_RELOAD_VALID",
	.pme_code = 0x00000300F6,
	.pme_short_desc = "DL1 reloaded due to Demand Load",
	.pme_long_desc = "DL1 reloaded due to Demand Load",
},
[ POWER9_PME_PM_L1_DEMAND_WRITE ] = {
	.pme_name = "PM_L1_DEMAND_WRITE",
	.pme_code = 0x000000408C,
	.pme_short_desc = "Instruction Demand sectors written into IL1",
	.pme_long_desc = "Instruction Demand sectors written into IL1",
},
[ POWER9_PME_PM_L1_ICACHE_MISS ] = {
	.pme_name = "PM_L1_ICACHE_MISS",
	.pme_code = 0x00000200FD,
	.pme_short_desc = "Demand iCache Miss",
	.pme_long_desc = "Demand iCache Miss",
},
[ POWER9_PME_PM_L1_ICACHE_RELOADED_ALL ] = {
	.pme_name = "PM_L1_ICACHE_RELOADED_ALL",
	.pme_code = 0x0000040012,
	.pme_short_desc = "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch",
	.pme_long_desc = "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch",
},
[ POWER9_PME_PM_L1_ICACHE_RELOADED_PREF ] = {
	.pme_name = "PM_L1_ICACHE_RELOADED_PREF",
	.pme_code = 0x0000030068,
	.pme_short_desc = "Counts all Icache prefetch reloads ( includes demand turned into prefetch)",
	.pme_long_desc = "Counts all Icache prefetch reloads ( includes demand turned into prefetch)",
},
[ POWER9_PME_PM_L1PF_L2MEMACC ] = {
	.pme_name = "PM_L1PF_L2MEMACC",
	.pme_code = 0x0000016890,
	.pme_short_desc = "Valid when first beat of data comes in for an L1PF where data came from memory",
	.pme_long_desc = "Valid when first beat of data comes in for an L1PF where data came from memory",
},
[ POWER9_PME_PM_L1_PREF ] = {
	.pme_name = "PM_L1_PREF",
	.pme_code = 0x0000020054,
	.pme_short_desc = "A data line was written to the L1 due to a hardware or software prefetch",
	.pme_long_desc = "A data line was written to the L1 due to a hardware or software prefetch",
},
[ POWER9_PME_PM_L1_SW_PREF ] = {
	.pme_name = "PM_L1_SW_PREF",
	.pme_code = 0x000000E880,
	.pme_short_desc = "Software L1 Prefetches, including SW Transient Prefetches",
	.pme_long_desc = "Software L1 Prefetches, including SW Transient Prefetches",
},
[ POWER9_PME_PM_L2_CASTOUT_MOD ] = {
	.pme_name = "PM_L2_CASTOUT_MOD",
	.pme_code = 0x0000016082,
	.pme_short_desc = "L2 Castouts - Modified (M,Mu,Me)",
	.pme_long_desc = "L2 Castouts - Modified (M,Mu,Me)",
},
[ POWER9_PME_PM_L2_CASTOUT_SHR ] = {
	.pme_name = "PM_L2_CASTOUT_SHR",
	.pme_code = 0x0000016882,
	.pme_short_desc = "L2 Castouts - Shared (Tx,Sx)",
	.pme_long_desc = "L2 Castouts - Shared (Tx,Sx)",
},
[ POWER9_PME_PM_L2_CHIP_PUMP ] = {
	.pme_name = "PM_L2_CHIP_PUMP",
	.pme_code = 0x0000046088,
	.pme_short_desc = "RC requests that were local (aka chip) pump attempts",
	.pme_long_desc = "RC requests that were local (aka chip) pump attempts",
},
[ POWER9_PME_PM_L2_DC_INV ] = {
	.pme_name = "PM_L2_DC_INV",
	.pme_code = 0x0000026882,
	.pme_short_desc = "D-cache invalidates sent over the reload bus to the core",
	.pme_long_desc = "D-cache invalidates sent over the reload bus to the core",
},
[ POWER9_PME_PM_L2_DISP_ALL_L2MISS ] = {
	.pme_name = "PM_L2_DISP_ALL_L2MISS",
	.pme_code = 0x0000046080,
	.pme_short_desc = "All successful Ld/St dispatches for this thread that were an L2 miss (excludes i_l2mru_tch_reqs)",
	.pme_long_desc = "All successful Ld/St dispatches for this thread that were an L2 miss (excludes i_l2mru_tch_reqs)",
},
[ POWER9_PME_PM_L2_GROUP_PUMP ] = {
	.pme_name = "PM_L2_GROUP_PUMP",
	.pme_code = 0x0000046888,
	.pme_short_desc = "RC requests that were on group (aka nodel) pump attempts",
	.pme_long_desc = "RC requests that were on group (aka nodel) pump attempts",
},
[ POWER9_PME_PM_L2_GRP_GUESS_CORRECT ] = {
	.pme_name = "PM_L2_GRP_GUESS_CORRECT",
	.pme_code = 0x0000026088,
	.pme_short_desc = "L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip)",
	.pme_long_desc = "L2 guess grp (GS or NNS) and guess was correct (data intra-group AND ^on-chip)",
},
[ POWER9_PME_PM_L2_GRP_GUESS_WRONG ] = {
	.pme_name = "PM_L2_GRP_GUESS_WRONG",
	.pme_code = 0x0000026888,
	.pme_short_desc = "L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group)",
	.pme_long_desc = "L2 guess grp (GS or NNS) and guess was not correct (ie data on-chip OR beyond-group)",
},
[ POWER9_PME_PM_L2_IC_INV ] = {
	.pme_name = "PM_L2_IC_INV",
	.pme_code = 0x0000026082,
	.pme_short_desc = "I-cache Invalidates sent over the realod bus to the core",
	.pme_long_desc = "I-cache Invalidates sent over the realod bus to the core",
},
[ POWER9_PME_PM_L2_INST_MISS ] = {
	.pme_name = "PM_L2_INST_MISS",
	.pme_code = 0x0000036880,
	.pme_short_desc = "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)",
	.pme_long_desc = "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)",
},
[ POWER9_PME_PM_L2_INST_MISS_ALT ] = {
	.pme_name = "PM_L2_INST_MISS_ALT",
	.pme_code = 0x000004609E,
	.pme_short_desc = "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)",
	.pme_long_desc = "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)",
},
[ POWER9_PME_PM_L2_INST ] = {
	.pme_name = "PM_L2_INST",
	.pme_code = 0x0000036080,
	.pme_short_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)",
	.pme_long_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)",
},
[ POWER9_PME_PM_L2_INST_ALT ] = {
	.pme_name = "PM_L2_INST_ALT",
	.pme_code = 0x000003609E,
	.pme_short_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)",
	.pme_long_desc = "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)",
},
[ POWER9_PME_PM_L2_LD_DISP ] = {
	.pme_name = "PM_L2_LD_DISP",
	.pme_code = 0x000001609E,
	.pme_short_desc = "All successful D-side load dispatches for this thread (L2 miss + L2 hits)",
	.pme_long_desc = "All successful D-side load dispatches for this thread (L2 miss + L2 hits)",
},
[ POWER9_PME_PM_L2_LD_DISP_ALT ] = {
	.pme_name = "PM_L2_LD_DISP_ALT",
	.pme_code = 0x0000036082,
	.pme_short_desc = "All successful I-or-D side load dispatches for this thread (excludes i_l2mru_tch_reqs)",
	.pme_long_desc = "All successful I-or-D side load dispatches for this thread (excludes i_l2mru_tch_reqs)",
},
[ POWER9_PME_PM_L2_LD_HIT ] = {
	.pme_name = "PM_L2_LD_HIT",
	.pme_code = 0x000002609E,
	.pme_short_desc = "All successful D-side load dispatches that were L2 hits for this thread",
	.pme_long_desc = "All successful D-side load dispatches that were L2 hits for this thread",
},
[ POWER9_PME_PM_L2_LD_HIT_ALT ] = {
	.pme_name = "PM_L2_LD_HIT_ALT",
	.pme_code = 0x0000036882,
	.pme_short_desc = "All successful I-or-D side load dispatches for this thread that were L2 hits (excludes i_l2mru_tch_reqs)",
	.pme_long_desc = "All successful I-or-D side load dispatches for this thread that were L2 hits (excludes i_l2mru_tch_reqs)",
},
[ POWER9_PME_PM_L2_LD_MISS_128B ] = {
	.pme_name = "PM_L2_LD_MISS_128B",
	.pme_code = 0x0000016092,
	.pme_short_desc = "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.",
	.pme_long_desc = "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.e., M=0)",
},
[ POWER9_PME_PM_L2_LD_MISS_64B ] = {
	.pme_name = "PM_L2_LD_MISS_64B",
	.pme_code = 0x0000026092,
	.pme_short_desc = "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B(i.",
	.pme_long_desc = "All successful D-side load dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B(i.e., M=1)",
},
[ POWER9_PME_PM_L2_LD_MISS ] = {
	.pme_name = "PM_L2_LD_MISS",
	.pme_code = 0x0000026080,
	.pme_short_desc = "All successful D-Side Load dispatches that were an L2 miss for this thread",
	.pme_long_desc = "All successful D-Side Load dispatches that were an L2 miss for this thread",
},
[ POWER9_PME_PM_L2_LD ] = {
	.pme_name = "PM_L2_LD",
	.pme_code = 0x0000016080,
	.pme_short_desc = "All successful D-side Load dispatches for this thread (L2 miss + L2 hits)",
	.pme_long_desc = "All successful D-side Load dispatches for this thread (L2 miss + L2 hits)",
},
[ POWER9_PME_PM_L2_LOC_GUESS_CORRECT ] = {
	.pme_name = "PM_L2_LOC_GUESS_CORRECT",
	.pme_code = 0x0000016088,
	.pme_short_desc = "L2 guess local (LNS) and guess was correct (ie data local)",
	.pme_long_desc = "L2 guess local (LNS) and guess was correct (ie data local)",
},
[ POWER9_PME_PM_L2_LOC_GUESS_WRONG ] = {
	.pme_name = "PM_L2_LOC_GUESS_WRONG",
	.pme_code = 0x0000016888,
	.pme_short_desc = "L2 guess local (LNS) and guess was not correct (ie data not on chip)",
	.pme_long_desc = "L2 guess local (LNS) and guess was not correct (ie data not on chip)",
},
[ POWER9_PME_PM_L2_RCLD_DISP_FAIL_ADDR ] = {
	.pme_name = "PM_L2_RCLD_DISP_FAIL_ADDR",
	.pme_code = 0x0000016884,
	.pme_short_desc = "All I-od-D side load dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ machine (excludes i_l2mru_tch_reqs)",
	.pme_long_desc = "All I-od-D side load dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ machine (excludes i_l2mru_tch_reqs)",
},
[ POWER9_PME_PM_L2_RCLD_DISP_FAIL_OTHER ] = {
	.pme_name = "PM_L2_RCLD_DISP_FAIL_OTHER",
	.pme_code = 0x0000026084,
	.pme_short_desc = "All I-or-D side load dispatch attempts for this thread that failed due to reason other than address collision (excludes i_l2mru_tch_reqs)",
	.pme_long_desc = "All I-or-D side load dispatch attempts for this thread that failed due to reason other than address collision (excludes i_l2mru_tch_reqs)",
},
[ POWER9_PME_PM_L2_RCLD_DISP ] = {
	.pme_name = "PM_L2_RCLD_DISP",
	.pme_code = 0x0000016084,
	.pme_short_desc = "All I-or-D side load dispatch attempts for this thread (excludes i_l2mru_tch_reqs)",
	.pme_long_desc = "All I-or-D side load dispatch attempts for this thread (excludes i_l2mru_tch_reqs)",
},
[ POWER9_PME_PM_L2_RCST_DISP_FAIL_ADDR ] = {
	.pme_name = "PM_L2_RCST_DISP_FAIL_ADDR",
	.pme_code = 0x0000036884,
	.pme_short_desc = "All D-side store dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ",
	.pme_long_desc = "All D-side store dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ",
},
[ POWER9_PME_PM_L2_RCST_DISP_FAIL_OTHER ] = {
	.pme_name = "PM_L2_RCST_DISP_FAIL_OTHER",
	.pme_code = 0x0000046084,
	.pme_short_desc = "All D-side store dispatch attempts for this thread that failed due to reason other than address collision",
	.pme_long_desc = "All D-side store dispatch attempts for this thread that failed due to reason other than address collision",
},
[ POWER9_PME_PM_L2_RCST_DISP ] = {
	.pme_name = "PM_L2_RCST_DISP",
	.pme_code = 0x0000036084,
	.pme_short_desc = "All D-side store dispatch attempts for this thread",
	.pme_long_desc = "All D-side store dispatch attempts for this thread",
},
[ POWER9_PME_PM_L2_RC_ST_DONE ] = {
	.pme_name = "PM_L2_RC_ST_DONE",
	.pme_code = 0x0000036086,
	.pme_short_desc = "RC did store to line that was Tx or Sx",
	.pme_long_desc = "RC did store to line that was Tx or Sx",
},
[ POWER9_PME_PM_L2_RTY_LD ] = {
	.pme_name = "PM_L2_RTY_LD",
	.pme_code = 0x000003688A,
	.pme_short_desc = "RC retries on PB for any load from core (excludes DCBFs)",
	.pme_long_desc = "RC retries on PB for any load from core (excludes DCBFs)",
},
[ POWER9_PME_PM_L2_RTY_LD_ALT ] = {
	.pme_name = "PM_L2_RTY_LD_ALT",
	.pme_code = 0x000003689E,
	.pme_short_desc = "RC retries on PB for any load from core (excludes DCBFs)",
	.pme_long_desc = "RC retries on PB for any load from core (excludes DCBFs)",
},
[ POWER9_PME_PM_L2_RTY_ST ] = {
	.pme_name = "PM_L2_RTY_ST",
	.pme_code = 0x000003608A,
	.pme_short_desc = "RC retries on PB for any store from core (excludes DCBFs)",
	.pme_long_desc = "RC retries on PB for any store from core (excludes DCBFs)",
},
[ POWER9_PME_PM_L2_RTY_ST_ALT ] = {
	.pme_name = "PM_L2_RTY_ST_ALT",
	.pme_code = 0x000004689E,
	.pme_short_desc = "RC retries on PB for any store from core (excludes DCBFs)",
	.pme_long_desc = "RC retries on PB for any store from core (excludes DCBFs)",
},
[ POWER9_PME_PM_L2_SN_M_RD_DONE ] = {
	.pme_name = "PM_L2_SN_M_RD_DONE",
	.pme_code = 0x0000046086,
	.pme_short_desc = "SNP dispatched for a read and was M (true M)",
	.pme_long_desc = "SNP dispatched for a read and was M (true M)",
},
[ POWER9_PME_PM_L2_SN_M_WR_DONE ] = {
	.pme_name = "PM_L2_SN_M_WR_DONE",
	.pme_code = 0x0000016086,
	.pme_short_desc = "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)",
	.pme_long_desc = "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)",
},
[ POWER9_PME_PM_L2_SN_M_WR_DONE_ALT ] = {
	.pme_name = "PM_L2_SN_M_WR_DONE_ALT",
	.pme_code = 0x0000046886,
	.pme_short_desc = "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)",
	.pme_long_desc = "SNP dispatched for a write and was M (true M); for DMA cacheinj this will pulse if rty/push is required (won't pulse if cacheinj is accepted)",
},
[ POWER9_PME_PM_L2_SN_SX_I_DONE ] = {
	.pme_name = "PM_L2_SN_SX_I_DONE",
	.pme_code = 0x0000036886,
	.pme_short_desc = "SNP dispatched and went from Sx to Ix",
	.pme_long_desc = "SNP dispatched and went from Sx to Ix",
},
[ POWER9_PME_PM_L2_ST_DISP ] = {
	.pme_name = "PM_L2_ST_DISP",
	.pme_code = 0x0000046082,
	.pme_short_desc = "All successful D-side store dispatches for this thread",
	.pme_long_desc = "All successful D-side store dispatches for this thread",
},
[ POWER9_PME_PM_L2_ST_DISP_ALT ] = {
	.pme_name = "PM_L2_ST_DISP_ALT",
	.pme_code = 0x000001689E,
	.pme_short_desc = "All successful D-side store dispatches for this thread (L2 miss + L2 hits)",
	.pme_long_desc = "All successful D-side store dispatches for this thread (L2 miss + L2 hits)",
},
[ POWER9_PME_PM_L2_ST_HIT ] = {
	.pme_name = "PM_L2_ST_HIT",
	.pme_code = 0x0000046882,
	.pme_short_desc = "All successful D-side store dispatches for this thread that were L2 hits",
	.pme_long_desc = "All successful D-side store dispatches for this thread that were L2 hits",
},
[ POWER9_PME_PM_L2_ST_HIT_ALT ] = {
	.pme_name = "PM_L2_ST_HIT_ALT",
	.pme_code = 0x000002689E,
	.pme_short_desc = "All successful D-side store dispatches that were L2 hits for this thread",
	.pme_long_desc = "All successful D-side store dispatches that were L2 hits for this thread",
},
[ POWER9_PME_PM_L2_ST_MISS_128B ] = {
	.pme_name = "PM_L2_ST_MISS_128B",
	.pme_code = 0x0000016892,
	.pme_short_desc = "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.",
	.pme_long_desc = "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 128B (i.e., M=0)",
},
[ POWER9_PME_PM_L2_ST_MISS_64B ] = {
	.pme_name = "PM_L2_ST_MISS_64B",
	.pme_code = 0x0000026892,
	.pme_short_desc = "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B (i.",
	.pme_long_desc = "All successful D-side store dispatches that were an L2 miss (NOT Sx,Tx,Mx) for this thread and the RC calculated the request should be for 64B (i.e., M=1)",
},
[ POWER9_PME_PM_L2_ST_MISS ] = {
	.pme_name = "PM_L2_ST_MISS",
	.pme_code = 0x0000026880,
	.pme_short_desc = "All successful D-Side Store dispatches that were an L2 miss for this thread",
	.pme_long_desc = "All successful D-Side Store dispatches that were an L2 miss for this thread",
},
[ POWER9_PME_PM_L2_ST ] = {
	.pme_name = "PM_L2_ST",
	.pme_code = 0x0000016880,
	.pme_short_desc = "All successful D-side store dispatches for this thread (L2 miss + L2 hits)",
	.pme_long_desc = "All successful D-side store dispatches for this thread (L2 miss + L2 hits)",
},
[ POWER9_PME_PM_L2_SYS_GUESS_CORRECT ] = {
	.pme_name = "PM_L2_SYS_GUESS_CORRECT",
	.pme_code = 0x0000036088,
	.pme_short_desc = "L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group)",
	.pme_long_desc = "L2 guess system (VGS or RNS) and guess was correct (ie data beyond-group)",
},
[ POWER9_PME_PM_L2_SYS_GUESS_WRONG ] = {
	.pme_name = "PM_L2_SYS_GUESS_WRONG",
	.pme_code = 0x0000036888,
	.pme_short_desc = "L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group)",
	.pme_long_desc = "L2 guess system (VGS or RNS) and guess was not correct (ie data ^beyond-group)",
},
[ POWER9_PME_PM_L2_SYS_PUMP ] = {
	.pme_name = "PM_L2_SYS_PUMP",
	.pme_code = 0x000004688A,
	.pme_short_desc = "RC requests that were system pump attempts",
	.pme_long_desc = "RC requests that were system pump attempts",
},
[ POWER9_PME_PM_L3_CI_HIT ] = {
	.pme_name = "PM_L3_CI_HIT",
	.pme_code = 0x00000260A2,
	.pme_short_desc = "L3 Castins Hit (total count)",
	.pme_long_desc = "L3 Castins Hit (total count)",
},
[ POWER9_PME_PM_L3_CI_MISS ] = {
	.pme_name = "PM_L3_CI_MISS",
	.pme_code = 0x00000268A2,
	.pme_short_desc = "L3 castins miss (total count)",
	.pme_long_desc = "L3 castins miss (total count)",
},
[ POWER9_PME_PM_L3_CINJ ] = {
	.pme_name = "PM_L3_CINJ",
	.pme_code = 0x00000368A4,
	.pme_short_desc = "L3 castin of cache inject",
	.pme_long_desc = "L3 castin of cache inject",
},
[ POWER9_PME_PM_L3_CI_USAGE ] = {
	.pme_name = "PM_L3_CI_USAGE",
	.pme_code = 0x00000168AC,
	.pme_short_desc = "Rotating sample of 16 CI or CO actives",
	.pme_long_desc = "Rotating sample of 16 CI or CO actives",
},
[ POWER9_PME_PM_L3_CO0_BUSY ] = {
	.pme_name = "PM_L3_CO0_BUSY",
	.pme_code = 0x00000368AC,
	.pme_short_desc = "Lifetime, sample of CO machine 0 valid",
	.pme_long_desc = "Lifetime, sample of CO machine 0 valid",
},
[ POWER9_PME_PM_L3_CO0_BUSY_ALT ] = {
	.pme_name = "PM_L3_CO0_BUSY_ALT",
	.pme_code = 0x00000468AC,
	.pme_short_desc = "Lifetime, sample of CO machine 0 valid",
	.pme_long_desc = "Lifetime, sample of CO machine 0 valid",
},
[ POWER9_PME_PM_L3_CO_L31 ] = {
	.pme_name = "PM_L3_CO_L31",
	.pme_code = 0x00000268A0,
	.pme_short_desc = "L3 CO to L3.",
	.pme_long_desc = "L3 CO to L3.1 OR of port 0 and 1 (lossy = may undercount if two cresps come in the same cyc)",
},
[ POWER9_PME_PM_L3_CO_LCO ] = {
	.pme_name = "PM_L3_CO_LCO",
	.pme_code = 0x00000360A4,
	.pme_short_desc = "Total L3 COs occurred on LCO L3.",
	.pme_long_desc = "Total L3 COs occurred on LCO L3.1 (good cresp, may end up in mem on a retry)",
},
[ POWER9_PME_PM_L3_CO_MEM ] = {
	.pme_name = "PM_L3_CO_MEM",
	.pme_code = 0x00000260A0,
	.pme_short_desc = "L3 CO to memory OR of port 0 and 1 (lossy = may undercount if two cresp come in the same cyc)",
	.pme_long_desc = "L3 CO to memory OR of port 0 and 1 (lossy = may undercount if two cresp come in the same cyc)",
},
[ POWER9_PME_PM_L3_CO_MEPF ] = {
	.pme_name = "PM_L3_CO_MEPF",
	.pme_code = 0x000003E05E,
	.pme_short_desc = "L3 castouts in Mepf state for this thread",
	.pme_long_desc = "L3 castouts in Mepf state for this thread",
},
[ POWER9_PME_PM_L3_CO_MEPF_ALT ] = {
	.pme_name = "PM_L3_CO_MEPF_ALT",
	.pme_code = 0x00000168A0,
	.pme_short_desc = "L3 CO of line in Mep state (includes casthrough to memory).",
	.pme_long_desc = "L3 CO of line in Mep state (includes casthrough to memory). The Mepf state indicates that a line was brought in to satisfy an L3 prefetch request",
},
[ POWER9_PME_PM_L3_CO ] = {
	.pme_name = "PM_L3_CO",
	.pme_code = 0x00000360A8,
	.pme_short_desc = "L3 castout occurring (does not include casthrough or log writes (cinj/dmaw))",
	.pme_long_desc = "L3 castout occurring (does not include casthrough or log writes (cinj/dmaw))",
},
[ POWER9_PME_PM_L3_GRP_GUESS_CORRECT ] = {
	.pme_name = "PM_L3_GRP_GUESS_CORRECT",
	.pme_code = 0x00000168B2,
	.pme_short_desc = "Initial scope=group (GS or NNS) and data from same group (near) (pred successful)",
	.pme_long_desc = "Initial scope=group (GS or NNS) and data from same group (near) (pred successful)",
},
[ POWER9_PME_PM_L3_GRP_GUESS_WRONG_HIGH ] = {
	.pme_name = "PM_L3_GRP_GUESS_WRONG_HIGH",
	.pme_code = 0x00000368B2,
	.pme_short_desc = "Initial scope=group (GS or NNS) but data from local node.",
	.pme_long_desc = "Initial scope=group (GS or NNS) but data from local node. Prediction too high",
},
[ POWER9_PME_PM_L3_GRP_GUESS_WRONG_LOW ] = {
	.pme_name = "PM_L3_GRP_GUESS_WRONG_LOW",
	.pme_code = 0x00000360B2,
	.pme_short_desc = "Initial scope=group (GS or NNS) but data from outside group (far or rem).",
	.pme_long_desc = "Initial scope=group (GS or NNS) but data from outside group (far or rem). Prediction too Low",
},
[ POWER9_PME_PM_L3_HIT ] = {
	.pme_name = "PM_L3_HIT",
	.pme_code = 0x00000160A4,
	.pme_short_desc = "L3 Hits (L2 miss hitting L3, including data/instrn/xlate)",
	.pme_long_desc = "L3 Hits (L2 miss hitting L3, including data/instrn/xlate)",
},
[ POWER9_PME_PM_L3_L2_CO_HIT ] = {
	.pme_name = "PM_L3_L2_CO_HIT",
	.pme_code = 0x00000360A2,
	.pme_short_desc = "L2 CO hits",
	.pme_long_desc = "L2 CO hits",
},
[ POWER9_PME_PM_L3_L2_CO_MISS ] = {
	.pme_name = "PM_L3_L2_CO_MISS",
	.pme_code = 0x00000368A2,
	.pme_short_desc = "L2 CO miss",
	.pme_long_desc = "L2 CO miss",
},
[ POWER9_PME_PM_L3_LAT_CI_HIT ] = {
	.pme_name = "PM_L3_LAT_CI_HIT",
	.pme_code = 0x00000460A2,
	.pme_short_desc = "L3 Lateral Castins Hit",
	.pme_long_desc = "L3 Lateral Castins Hit",
},
[ POWER9_PME_PM_L3_LAT_CI_MISS ] = {
	.pme_name = "PM_L3_LAT_CI_MISS",
	.pme_code = 0x00000468A2,
	.pme_short_desc = "L3 Lateral Castins Miss",
	.pme_long_desc = "L3 Lateral Castins Miss",
},
[ POWER9_PME_PM_L3_LD_HIT ] = {
	.pme_name = "PM_L3_LD_HIT",
	.pme_code = 0x00000260A4,
	.pme_short_desc = "L3 Hits for demand LDs",
	.pme_long_desc = "L3 Hits for demand LDs",
},
[ POWER9_PME_PM_L3_LD_MISS ] = {
	.pme_name = "PM_L3_LD_MISS",
	.pme_code = 0x00000268A4,
	.pme_short_desc = "L3 Misses for demand LDs",
	.pme_long_desc = "L3 Misses for demand LDs",
},
[ POWER9_PME_PM_L3_LD_PREF ] = {
	.pme_name = "PM_L3_LD_PREF",
	.pme_code = 0x000000F0B0,
	.pme_short_desc = "L3 load prefetch, sourced from a hardware or software stream, was sent to the nest",
	.pme_long_desc = "L3 load prefetch, sourced from a hardware or software stream, was sent to the nest",
},
[ POWER9_PME_PM_L3_LOC_GUESS_CORRECT ] = {
	.pme_name = "PM_L3_LOC_GUESS_CORRECT",
	.pme_code = 0x00000160B2,
	.pme_short_desc = "initial scope=node/chip (LNS) and data from local node (local) (pred successful) - always PFs only",
	.pme_long_desc = "initial scope=node/chip (LNS) and data from local node (local) (pred successful) - always PFs only",
},
[ POWER9_PME_PM_L3_LOC_GUESS_WRONG ] = {
	.pme_name = "PM_L3_LOC_GUESS_WRONG",
	.pme_code = 0x00000268B2,
	.pme_short_desc = "Initial scope=node (LNS) but data from out side local node (near or far or rem).",
	.pme_long_desc = "Initial scope=node (LNS) but data from out side local node (near or far or rem). Prediction too Low",
},
[ POWER9_PME_PM_L3_MISS ] = {
	.pme_name = "PM_L3_MISS",
	.pme_code = 0x00000168A4,
	.pme_short_desc = "L3 Misses (L2 miss also missing L3, including data/instrn/xlate)",
	.pme_long_desc = "L3 Misses (L2 miss also missing L3, including data/instrn/xlate)",
},
[ POWER9_PME_PM_L3_P0_CO_L31 ] = {
	.pme_name = "PM_L3_P0_CO_L31",
	.pme_code = 0x00000460AA,
	.pme_short_desc = "L3 CO to L3.",
	.pme_long_desc = "L3 CO to L3.1 (LCO) port 0 with or without data",
},
[ POWER9_PME_PM_L3_P0_CO_MEM ] = {
	.pme_name = "PM_L3_P0_CO_MEM",
	.pme_code = 0x00000360AA,
	.pme_short_desc = "L3 CO to memory port 0 with or without data",
	.pme_long_desc = "L3 CO to memory port 0 with or without data",
},
[ POWER9_PME_PM_L3_P0_CO_RTY ] = {
	.pme_name = "PM_L3_P0_CO_RTY",
	.pme_code = 0x00000360AE,
	.pme_short_desc = "L3 CO received retry port 0 (memory only), every retry counted",
	.pme_long_desc = "L3 CO received retry port 0 (memory only), every retry counted",
},
[ POWER9_PME_PM_L3_P0_CO_RTY_ALT ] = {
	.pme_name = "PM_L3_P0_CO_RTY_ALT",
	.pme_code = 0x00000460AE,
	.pme_short_desc = "L3 CO received retry port 2 (memory only), every retry counted",
	.pme_long_desc = "L3 CO received retry port 2 (memory only), every retry counted",
},
[ POWER9_PME_PM_L3_P0_GRP_PUMP ] = {
	.pme_name = "PM_L3_P0_GRP_PUMP",
	.pme_code = 0x00000260B0,
	.pme_short_desc = "L3 PF sent with grp scope port 0, counts even retried requests",
	.pme_long_desc = "L3 PF sent with grp scope port 0, counts even retried requests",
},
[ POWER9_PME_PM_L3_P0_LCO_DATA ] = {
	.pme_name = "PM_L3_P0_LCO_DATA",
	.pme_code = 0x00000260AA,
	.pme_short_desc = "LCO sent with data port 0",
	.pme_long_desc = "LCO sent with data port 0",
},
[ POWER9_PME_PM_L3_P0_LCO_NO_DATA ] = {
	.pme_name = "PM_L3_P0_LCO_NO_DATA",
	.pme_code = 0x00000160AA,
	.pme_short_desc = "Dataless L3 LCO sent port 0",
	.pme_long_desc = "Dataless L3 LCO sent port 0",
},
[ POWER9_PME_PM_L3_P0_LCO_RTY ] = {
	.pme_name = "PM_L3_P0_LCO_RTY",
	.pme_code = 0x00000160B4,
	.pme_short_desc = "L3 initiated LCO received retry on port 0 (can try 4 times)",
	.pme_long_desc = "L3 initiated LCO received retry on port 0 (can try 4 times)",
},
[ POWER9_PME_PM_L3_P0_NODE_PUMP ] = {
	.pme_name = "PM_L3_P0_NODE_PUMP",
	.pme_code = 0x00000160B0,
	.pme_short_desc = "L3 PF sent with nodal scope port 0, counts even retried requests",
	.pme_long_desc = "L3 PF sent with nodal scope port 0, counts even retried requests",
},
[ POWER9_PME_PM_L3_P0_PF_RTY ] = {
	.pme_name = "PM_L3_P0_PF_RTY",
	.pme_code = 0x00000160AE,
	.pme_short_desc = "L3 PF received retry port 0, every retry counted",
	.pme_long_desc = "L3 PF received retry port 0, every retry counted",
},
[ POWER9_PME_PM_L3_P0_PF_RTY_ALT ] = {
	.pme_name = "PM_L3_P0_PF_RTY_ALT",
	.pme_code = 0x00000260AE,
	.pme_short_desc = "L3 PF received retry port 2, every retry counted",
	.pme_long_desc = "L3 PF received retry port 2, every retry counted",
},
[ POWER9_PME_PM_L3_P0_SYS_PUMP ] = {
	.pme_name = "PM_L3_P0_SYS_PUMP",
	.pme_code = 0x00000360B0,
	.pme_short_desc = "L3 PF sent with sys scope port 0, counts even retried requests",
	.pme_long_desc = "L3 PF sent with sys scope port 0, counts even retried requests",
},
[ POWER9_PME_PM_L3_P1_CO_L31 ] = {
	.pme_name = "PM_L3_P1_CO_L31",
	.pme_code = 0x00000468AA,
	.pme_short_desc = "L3 CO to L3.",
	.pme_long_desc = "L3 CO to L3.1 (LCO) port 1 with or without data",
},
[ POWER9_PME_PM_L3_P1_CO_MEM ] = {
	.pme_name = "PM_L3_P1_CO_MEM",
	.pme_code = 0x00000368AA,
	.pme_short_desc = "L3 CO to memory port 1 with or without data",
	.pme_long_desc = "L3 CO to memory port 1 with or without data",
},
[ POWER9_PME_PM_L3_P1_CO_RTY ] = {
	.pme_name = "PM_L3_P1_CO_RTY",
	.pme_code = 0x00000368AE,
	.pme_short_desc = "L3 CO received retry port 1 (memory only), every retry counted",
	.pme_long_desc = "L3 CO received retry port 1 (memory only), every retry counted",
},
[ POWER9_PME_PM_L3_P1_CO_RTY_ALT ] = {
	.pme_name = "PM_L3_P1_CO_RTY_ALT",
	.pme_code = 0x00000468AE,
	.pme_short_desc = "L3 CO received retry port 3 (memory only), every retry counted",
	.pme_long_desc = "L3 CO received retry port 3 (memory only), every retry counted",
},
[ POWER9_PME_PM_L3_P1_GRP_PUMP ] = {
	.pme_name = "PM_L3_P1_GRP_PUMP",
	.pme_code = 0x00000268B0,
	.pme_short_desc = "L3 PF sent with grp scope port 1, counts even retried requests",
	.pme_long_desc = "L3 PF sent with grp scope port 1, counts even retried requests",
},
[ POWER9_PME_PM_L3_P1_LCO_DATA ] = {
	.pme_name = "PM_L3_P1_LCO_DATA",
	.pme_code = 0x00000268AA,
	.pme_short_desc = "LCO sent with data port 1",
	.pme_long_desc = "LCO sent with data port 1",
},
[ POWER9_PME_PM_L3_P1_LCO_NO_DATA ] = {
	.pme_name = "PM_L3_P1_LCO_NO_DATA",
	.pme_code = 0x00000168AA,
	.pme_short_desc = "Dataless L3 LCO sent port 1",
	.pme_long_desc = "Dataless L3 LCO sent port 1",
},
[ POWER9_PME_PM_L3_P1_LCO_RTY ] = {
	.pme_name = "PM_L3_P1_LCO_RTY",
	.pme_code = 0x00000168B4,
	.pme_short_desc = "L3 initiated LCO received retry on port 1 (can try 4 times)",
	.pme_long_desc = "L3 initiated LCO received retry on port 1 (can try 4 times)",
},
[ POWER9_PME_PM_L3_P1_NODE_PUMP ] = {
	.pme_name = "PM_L3_P1_NODE_PUMP",
	.pme_code = 0x00000168B0,
	.pme_short_desc = "L3 PF sent with nodal scope port 1, counts even retried requests",
	.pme_long_desc = "L3 PF sent with nodal scope port 1, counts even retried requests",
},
[ POWER9_PME_PM_L3_P1_PF_RTY ] = {
	.pme_name = "PM_L3_P1_PF_RTY",
	.pme_code = 0x00000168AE,
	.pme_short_desc = "L3 PF received retry port 1, every retry counted",
	.pme_long_desc = "L3 PF received retry port 1, every retry counted",
},
[ POWER9_PME_PM_L3_P1_PF_RTY_ALT ] = {
	.pme_name = "PM_L3_P1_PF_RTY_ALT",
	.pme_code = 0x00000268AE,
	.pme_short_desc = "L3 PF received retry port 3, every retry counted",
	.pme_long_desc = "L3 PF received retry port 3, every retry counted",
},
[ POWER9_PME_PM_L3_P1_SYS_PUMP ] = {
	.pme_name = "PM_L3_P1_SYS_PUMP",
	.pme_code = 0x00000368B0,
	.pme_short_desc = "L3 PF sent with sys scope port 1, counts even retried requests",
	.pme_long_desc = "L3 PF sent with sys scope port 1, counts even retried requests",
},
[ POWER9_PME_PM_L3_P2_LCO_RTY ] = {
	.pme_name = "PM_L3_P2_LCO_RTY",
	.pme_code = 0x00000260B4,
	.pme_short_desc = "L3 initiated LCO received retry on port 2 (can try 4 times)",
	.pme_long_desc = "L3 initiated LCO received retry on port 2 (can try 4 times)",
},
[ POWER9_PME_PM_L3_P3_LCO_RTY ] = {
	.pme_name = "PM_L3_P3_LCO_RTY",
	.pme_code = 0x00000268B4,
	.pme_short_desc = "L3 initiated LCO received retry on port 3 (can try 4 times)",
	.pme_long_desc = "L3 initiated LCO received retry on port 3 (can try 4 times)",
},
[ POWER9_PME_PM_L3_PF0_BUSY ] = {
	.pme_name = "PM_L3_PF0_BUSY",
	.pme_code = 0x00000360B4,
	.pme_short_desc = "Lifetime, sample of PF machine 0 valid",
	.pme_long_desc = "Lifetime, sample of PF machine 0 valid",
},
[ POWER9_PME_PM_L3_PF0_BUSY_ALT ] = {
	.pme_name = "PM_L3_PF0_BUSY_ALT",
	.pme_code = 0x00000460B4,
	.pme_short_desc = "Lifetime, sample of PF machine 0 valid",
	.pme_long_desc = "Lifetime, sample of PF machine 0 valid",
},
[ POWER9_PME_PM_L3_PF_HIT_L3 ] = {
	.pme_name = "PM_L3_PF_HIT_L3",
	.pme_code = 0x00000260A8,
	.pme_short_desc = "L3 PF hit in L3 (abandoned)",
	.pme_long_desc = "L3 PF hit in L3 (abandoned)",
},
[ POWER9_PME_PM_L3_PF_MISS_L3 ] = {
	.pme_name = "PM_L3_PF_MISS_L3",
	.pme_code = 0x00000160A0,
	.pme_short_desc = "L3 PF missed in L3",
	.pme_long_desc = "L3 PF missed in L3",
},
[ POWER9_PME_PM_L3_PF_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_L3_PF_OFF_CHIP_CACHE",
	.pme_code = 0x00000368A0,
	.pme_short_desc = "L3 PF from Off chip cache",
	.pme_long_desc = "L3 PF from Off chip cache",
},
[ POWER9_PME_PM_L3_PF_OFF_CHIP_MEM ] = {
	.pme_name = "PM_L3_PF_OFF_CHIP_MEM",
	.pme_code = 0x00000468A0,
	.pme_short_desc = "L3 PF from Off chip memory",
	.pme_long_desc = "L3 PF from Off chip memory",
},
[ POWER9_PME_PM_L3_PF_ON_CHIP_CACHE ] = {
	.pme_name = "PM_L3_PF_ON_CHIP_CACHE",
	.pme_code = 0x00000360A0,
	.pme_short_desc = "L3 PF from On chip cache",
	.pme_long_desc = "L3 PF from On chip cache",
},
[ POWER9_PME_PM_L3_PF_ON_CHIP_MEM ] = {
	.pme_name = "PM_L3_PF_ON_CHIP_MEM",
	.pme_code = 0x00000460A0,
	.pme_short_desc = "L3 PF from On chip memory",
	.pme_long_desc = "L3 PF from On chip memory",
},
[ POWER9_PME_PM_L3_PF_USAGE ] = {
	.pme_name = "PM_L3_PF_USAGE",
	.pme_code = 0x00000260AC,
	.pme_short_desc = "Rotating sample of 32 PF actives",
	.pme_long_desc = "Rotating sample of 32 PF actives",
},
[ POWER9_PME_PM_L3_RD0_BUSY ] = {
	.pme_name = "PM_L3_RD0_BUSY",
	.pme_code = 0x00000368B4,
	.pme_short_desc = "Lifetime, sample of RD machine 0 valid",
	.pme_long_desc = "Lifetime, sample of RD machine 0 valid",
},
[ POWER9_PME_PM_L3_RD0_BUSY_ALT ] = {
	.pme_name = "PM_L3_RD0_BUSY_ALT",
	.pme_code = 0x00000468B4,
	.pme_short_desc = "Lifetime, sample of RD machine 0 valid",
	.pme_long_desc = "Lifetime, sample of RD machine 0 valid",
},
[ POWER9_PME_PM_L3_RD_USAGE ] = {
	.pme_name = "PM_L3_RD_USAGE",
	.pme_code = 0x00000268AC,
	.pme_short_desc = "Rotating sample of 16 RD actives",
	.pme_long_desc = "Rotating sample of 16 RD actives",
},
[ POWER9_PME_PM_L3_SN0_BUSY ] = {
	.pme_name = "PM_L3_SN0_BUSY",
	.pme_code = 0x00000360AC,
	.pme_short_desc = "Lifetime, sample of snooper machine 0 valid",
	.pme_long_desc = "Lifetime, sample of snooper machine 0 valid",
},
[ POWER9_PME_PM_L3_SN0_BUSY_ALT ] = {
	.pme_name = "PM_L3_SN0_BUSY_ALT",
	.pme_code = 0x00000460AC,
	.pme_short_desc = "Lifetime, sample of snooper machine 0 valid",
	.pme_long_desc = "Lifetime, sample of snooper machine 0 valid",
},
[ POWER9_PME_PM_L3_SN_USAGE ] = {
	.pme_name = "PM_L3_SN_USAGE",
	.pme_code = 0x00000160AC,
	.pme_short_desc = "Rotating sample of 16 snoop valids",
	.pme_long_desc = "Rotating sample of 16 snoop valids",
},
[ POWER9_PME_PM_L3_SW_PREF ] = {
	.pme_name = "PM_L3_SW_PREF",
	.pme_code = 0x000000F8B0,
	.pme_short_desc = "L3 load prefetch, sourced from a software prefetch stream, was sent to the nest",
	.pme_long_desc = "L3 load prefetch, sourced from a software prefetch stream, was sent to the nest",
},
[ POWER9_PME_PM_L3_SYS_GUESS_CORRECT ] = {
	.pme_name = "PM_L3_SYS_GUESS_CORRECT",
	.pme_code = 0x00000260B2,
	.pme_short_desc = "Initial scope=system (VGS or RNS) and data from outside group (far or rem)(pred successful)",
	.pme_long_desc = "Initial scope=system (VGS or RNS) and data from outside group (far or rem)(pred successful)",
},
[ POWER9_PME_PM_L3_SYS_GUESS_WRONG ] = {
	.pme_name = "PM_L3_SYS_GUESS_WRONG",
	.pme_code = 0x00000460B2,
	.pme_short_desc = "Initial scope=system (VGS or RNS) but data from local or near.",
	.pme_long_desc = "Initial scope=system (VGS or RNS) but data from local or near. Prediction too high",
},
[ POWER9_PME_PM_L3_TRANS_PF ] = {
	.pme_name = "PM_L3_TRANS_PF",
	.pme_code = 0x00000468A4,
	.pme_short_desc = "L3 Transient prefetch received from L2",
	.pme_long_desc = "L3 Transient prefetch received from L2",
},
[ POWER9_PME_PM_L3_WI0_BUSY ] = {
	.pme_name = "PM_L3_WI0_BUSY",
	.pme_code = 0x00000160B6,
	.pme_short_desc = "Rotating sample of 8 WI valid",
	.pme_long_desc = "Rotating sample of 8 WI valid",
},
[ POWER9_PME_PM_L3_WI0_BUSY_ALT ] = {
	.pme_name = "PM_L3_WI0_BUSY_ALT",
	.pme_code = 0x00000260B6,
	.pme_short_desc = "Rotating sample of 8 WI valid (duplicate)",
	.pme_long_desc = "Rotating sample of 8 WI valid (duplicate)",
},
[ POWER9_PME_PM_L3_WI_USAGE ] = {
	.pme_name = "PM_L3_WI_USAGE",
	.pme_code = 0x00000168A8,
	.pme_short_desc = "Lifetime, sample of Write Inject machine 0 valid",
	.pme_long_desc = "Lifetime, sample of Write Inject machine 0 valid",
},
[ POWER9_PME_PM_LARX_FIN ] = {
	.pme_name = "PM_LARX_FIN",
	.pme_code = 0x000003C058,
	.pme_short_desc = "Larx finished",
	.pme_long_desc = "Larx finished",
},
[ POWER9_PME_PM_LD_CMPL ] = {
	.pme_name = "PM_LD_CMPL",
	.pme_code = 0x000004003E,
	.pme_short_desc = "count of Loads completed",
	.pme_long_desc = "count of Loads completed",
},
[ POWER9_PME_PM_LD_L3MISS_PEND_CYC ] = {
	.pme_name = "PM_LD_L3MISS_PEND_CYC",
	.pme_code = 0x0000010062,
	.pme_short_desc = "Cycles L3 miss was pending for this thread",
	.pme_long_desc = "Cycles L3 miss was pending for this thread",
},
[ POWER9_PME_PM_LD_MISS_L1_FIN ] = {
	.pme_name = "PM_LD_MISS_L1_FIN",
	.pme_code = 0x000002C04E,
	.pme_short_desc = "Number of load instructions that finished with an L1 miss.",
	.pme_long_desc = "Number of load instructions that finished with an L1 miss. Note that even if a load spans multiple slices this event will increment only once per load op.",
},
/* See also alternate entries for 000003E054 / POWER9_PME_PM_LD_MISS_L1 with code(s) 00000400F0 at the bottom of this table. \n */
[ POWER9_PME_PM_LD_MISS_L1 ] = {
	.pme_name = "PM_LD_MISS_L1",
	.pme_code = 0x000003E054,
	.pme_short_desc = "Load Missed L1, counted at execution time (can be greater than loads finished).",
	.pme_long_desc = "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.",
},
[ POWER9_PME_PM_LD_REF_L1 ] = {
	.pme_name = "PM_LD_REF_L1",
	.pme_code = 0x00000100FC,
	.pme_short_desc = "All L1 D cache load references counted at finish, gated by reject",
	.pme_long_desc = "All L1 D cache load references counted at finish, gated by reject",
},
[ POWER9_PME_PM_LINK_STACK_CORRECT ] = {
	.pme_name = "PM_LINK_STACK_CORRECT",
	.pme_code = 0x00000058A0,
	.pme_short_desc = "Link stack predicts right address",
	.pme_long_desc = "Link stack predicts right address",
},
[ POWER9_PME_PM_LINK_STACK_INVALID_PTR ] = {
	.pme_name = "PM_LINK_STACK_INVALID_PTR",
	.pme_code = 0x0000005898,
	.pme_short_desc = "It is most often caused by certain types of flush where the pointer is not available.",
	.pme_long_desc = "It is most often caused by certain types of flush where the pointer is not available. Can result in the data in the link stack becoming unusable.",
},
[ POWER9_PME_PM_LINK_STACK_WRONG_ADD_PRED ] = {
	.pme_name = "PM_LINK_STACK_WRONG_ADD_PRED",
	.pme_code = 0x0000005098,
	.pme_short_desc = "Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions",
	.pme_long_desc = "Link stack predicts wrong address, because of link stack design limitation or software violating the coding conventions",
},
[ POWER9_PME_PM_LMQ_EMPTY_CYC ] = {
	.pme_name = "PM_LMQ_EMPTY_CYC",
	.pme_code = 0x000002E05E,
	.pme_short_desc = "Cycles in which the LMQ has no pending load misses for this thread",
	.pme_long_desc = "Cycles in which the LMQ has no pending load misses for this thread",
},
[ POWER9_PME_PM_LMQ_MERGE ] = {
	.pme_name = "PM_LMQ_MERGE",
	.pme_code = 0x000001002E,
	.pme_short_desc = "A demand miss collides with a prefetch for the same line",
	.pme_long_desc = "A demand miss collides with a prefetch for the same line",
},
[ POWER9_PME_PM_LRQ_REJECT ] = {
	.pme_name = "PM_LRQ_REJECT",
	.pme_code = 0x000002E05A,
	.pme_short_desc = "Internal LSU reject from LRQ.",
	.pme_long_desc = "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects",
},
[ POWER9_PME_PM_LS0_DC_COLLISIONS ] = {
	.pme_name = "PM_LS0_DC_COLLISIONS",
	.pme_code = 0x000000D090,
	.pme_short_desc = "Read-write data cache collisions",
	.pme_long_desc = "Read-write data cache collisions",
},
[ POWER9_PME_PM_LS0_ERAT_MISS_PREF ] = {
	.pme_name = "PM_LS0_ERAT_MISS_PREF",
	.pme_code = 0x000000E084,
	.pme_short_desc = "LS0 Erat miss due to prefetch",
	.pme_long_desc = "LS0 Erat miss due to prefetch",
},
[ POWER9_PME_PM_LS0_LAUNCH_HELD_PREF ] = {
	.pme_name = "PM_LS0_LAUNCH_HELD_PREF",
	.pme_code = 0x000000C09C,
	.pme_short_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle",
	.pme_long_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle",
},
[ POWER9_PME_PM_LS0_PTE_TABLEWALK_CYC ] = {
	.pme_name = "PM_LS0_PTE_TABLEWALK_CYC",
	.pme_code = 0x000000E0BC,
	.pme_short_desc = "Cycles when a tablewalk is pending on this thread on table 0",
	.pme_long_desc = "Cycles when a tablewalk is pending on this thread on table 0",
},
[ POWER9_PME_PM_LS0_TM_DISALLOW ] = {
	.pme_name = "PM_LS0_TM_DISALLOW",
	.pme_code = 0x000000E0B4,
	.pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
	.pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
},
[ POWER9_PME_PM_LS0_UNALIGNED_LD ] = {
	.pme_name = "PM_LS0_UNALIGNED_LD",
	.pme_code = 0x000000C094,
	.pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.",
	.pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
},
[ POWER9_PME_PM_LS0_UNALIGNED_ST ] = {
	.pme_name = "PM_LS0_UNALIGNED_ST",
	.pme_code = 0x000000F0B8,
	.pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.",
	.pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
},
[ POWER9_PME_PM_LS1_DC_COLLISIONS ] = {
	.pme_name = "PM_LS1_DC_COLLISIONS",
	.pme_code = 0x000000D890,
	.pme_short_desc = "Read-write data cache collisions",
	.pme_long_desc = "Read-write data cache collisions",
},
[ POWER9_PME_PM_LS1_ERAT_MISS_PREF ] = {
	.pme_name = "PM_LS1_ERAT_MISS_PREF",
	.pme_code = 0x000000E884,
	.pme_short_desc = "LS1 Erat miss due to prefetch",
	.pme_long_desc = "LS1 Erat miss due to prefetch",
},
[ POWER9_PME_PM_LS1_LAUNCH_HELD_PREF ] = {
	.pme_name = "PM_LS1_LAUNCH_HELD_PREF",
	.pme_code = 0x000000C89C,
	.pme_short_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle",
	.pme_long_desc = "Number of times a load or store instruction was unable to launch/relaunch because a high priority prefetch used that relaunch cycle",
},
[ POWER9_PME_PM_LS1_PTE_TABLEWALK_CYC ] = {
	.pme_name = "PM_LS1_PTE_TABLEWALK_CYC",
	.pme_code = 0x000000E8BC,
	.pme_short_desc = "Cycles when a tablewalk is pending on this thread on table 1",
	.pme_long_desc = "Cycles when a tablewalk is pending on this thread on table 1",
},
[ POWER9_PME_PM_LS1_TM_DISALLOW ] = {
	.pme_name = "PM_LS1_TM_DISALLOW",
	.pme_code = 0x000000E8B4,
	.pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
	.pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
},
[ POWER9_PME_PM_LS1_UNALIGNED_LD ] = {
	.pme_name = "PM_LS1_UNALIGNED_LD",
	.pme_code = 0x000000C894,
	.pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.",
	.pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
},
[ POWER9_PME_PM_LS1_UNALIGNED_ST ] = {
	.pme_name = "PM_LS1_UNALIGNED_ST",
	.pme_code = 0x000000F8B8,
	.pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.",
	.pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
},
[ POWER9_PME_PM_LS2_DC_COLLISIONS ] = {
	.pme_name = "PM_LS2_DC_COLLISIONS",
	.pme_code = 0x000000D094,
	.pme_short_desc = "Read-write data cache collisions",
	.pme_long_desc = "Read-write data cache collisions",
},
[ POWER9_PME_PM_LS2_ERAT_MISS_PREF ] = {
	.pme_name = "PM_LS2_ERAT_MISS_PREF",
	.pme_code = 0x000000E088,
	.pme_short_desc = "LS0 Erat miss due to prefetch",
	.pme_long_desc = "LS0 Erat miss due to prefetch",
},
[ POWER9_PME_PM_LS2_TM_DISALLOW ] = {
	.pme_name = "PM_LS2_TM_DISALLOW",
	.pme_code = 0x000000E0B8,
	.pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
	.pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
},
[ POWER9_PME_PM_LS2_UNALIGNED_LD ] = {
	.pme_name = "PM_LS2_UNALIGNED_LD",
	.pme_code = 0x000000C098,
	.pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.",
	.pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
},
[ POWER9_PME_PM_LS2_UNALIGNED_ST ] = {
	.pme_name = "PM_LS2_UNALIGNED_ST",
	.pme_code = 0x000000F0BC,
	.pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.",
	.pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
},
[ POWER9_PME_PM_LS3_DC_COLLISIONS ] = {
	.pme_name = "PM_LS3_DC_COLLISIONS",
	.pme_code = 0x000000D894,
	.pme_short_desc = "Read-write data cache collisions",
	.pme_long_desc = "Read-write data cache collisions",
},
[ POWER9_PME_PM_LS3_ERAT_MISS_PREF ] = {
	.pme_name = "PM_LS3_ERAT_MISS_PREF",
	.pme_code = 0x000000E888,
	.pme_short_desc = "LS1 Erat miss due to prefetch",
	.pme_long_desc = "LS1 Erat miss due to prefetch",
},
[ POWER9_PME_PM_LS3_TM_DISALLOW ] = {
	.pme_name = "PM_LS3_TM_DISALLOW",
	.pme_code = 0x000000E8B8,
	.pme_short_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
	.pme_long_desc = "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it",
},
[ POWER9_PME_PM_LS3_UNALIGNED_LD ] = {
	.pme_name = "PM_LS3_UNALIGNED_LD",
	.pme_code = 0x000000C898,
	.pme_short_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size.",
	.pme_long_desc = "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
},
[ POWER9_PME_PM_LS3_UNALIGNED_ST ] = {
	.pme_name = "PM_LS3_UNALIGNED_ST",
	.pme_code = 0x000000F8BC,
	.pme_short_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size.",
	.pme_long_desc = "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty",
},
[ POWER9_PME_PM_LSU0_1_LRQF_FULL_CYC ] = {
	.pme_name = "PM_LSU0_1_LRQF_FULL_CYC",
	.pme_code = 0x000000D0BC,
	.pme_short_desc = "Counts the number of cycles the LRQF is full.",
	.pme_long_desc = "Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ",
},
[ POWER9_PME_PM_LSU0_ERAT_HIT ] = {
	.pme_name = "PM_LSU0_ERAT_HIT",
	.pme_code = 0x000000E08C,
	.pme_short_desc = "Primary ERAT hit.",
	.pme_long_desc = "Primary ERAT hit. There is no secondary ERAT",
},
[ POWER9_PME_PM_LSU0_FALSE_LHS ] = {
	.pme_name = "PM_LSU0_FALSE_LHS",
	.pme_code = 0x000000C0A0,
	.pme_short_desc = "False LHS match detected",
	.pme_long_desc = "False LHS match detected",
},
[ POWER9_PME_PM_LSU0_L1_CAM_CANCEL ] = {
	.pme_name = "PM_LSU0_L1_CAM_CANCEL",
	.pme_code = 0x000000F090,
	.pme_short_desc = "ls0 l1 tm cam cancel",
	.pme_long_desc = "ls0 l1 tm cam cancel",
},
[ POWER9_PME_PM_LSU0_LDMX_FIN ] = {
	.pme_name = "PM_LSU0_LDMX_FIN",
	.pme_code = 0x000000D088,
	.pme_short_desc = "New P9 instruction LDMX.",
	.pme_long_desc = "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491):  The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region.  This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]).",
},
[ POWER9_PME_PM_LSU0_LMQ_S0_VALID ] = {
	.pme_name = "PM_LSU0_LMQ_S0_VALID",
	.pme_code = 0x000000D8B8,
	.pme_short_desc = "Slot 0 of LMQ valid",
	.pme_long_desc = "Slot 0 of LMQ valid",
},
[ POWER9_PME_PM_LSU0_LRQ_S0_VALID_CYC ] = {
	.pme_name = "PM_LSU0_LRQ_S0_VALID_CYC",
	.pme_code = 0x000000D8B4,
	.pme_short_desc = "Slot 0 of LRQ valid",
	.pme_long_desc = "Slot 0 of LRQ valid",
},
[ POWER9_PME_PM_LSU0_SET_MPRED ] = {
	.pme_name = "PM_LSU0_SET_MPRED",
	.pme_code = 0x000000D080,
	.pme_short_desc = "Set prediction(set-p) miss.",
	.pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table",
},
[ POWER9_PME_PM_LSU0_SRQ_S0_VALID_CYC ] = {
	.pme_name = "PM_LSU0_SRQ_S0_VALID_CYC",
	.pme_code = 0x000000D0B4,
	.pme_short_desc = "Slot 0 of SRQ valid",
	.pme_long_desc = "Slot 0 of SRQ valid",
},
[ POWER9_PME_PM_LSU0_STORE_REJECT ] = {
	.pme_name = "PM_LSU0_STORE_REJECT",
	.pme_code = 0x000000F088,
	.pme_short_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
	.pme_long_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
},
[ POWER9_PME_PM_LSU0_TM_L1_HIT ] = {
	.pme_name = "PM_LSU0_TM_L1_HIT",
	.pme_code = 0x000000E094,
	.pme_short_desc = "Load tm hit in L1",
	.pme_long_desc = "Load tm hit in L1",
},
[ POWER9_PME_PM_LSU0_TM_L1_MISS ] = {
	.pme_name = "PM_LSU0_TM_L1_MISS",
	.pme_code = 0x000000E09C,
	.pme_short_desc = "Load tm L1 miss",
	.pme_long_desc = "Load tm L1 miss",
},
[ POWER9_PME_PM_LSU1_ERAT_HIT ] = {
	.pme_name = "PM_LSU1_ERAT_HIT",
	.pme_code = 0x000000E88C,
	.pme_short_desc = "Primary ERAT hit.",
	.pme_long_desc = "Primary ERAT hit. There is no secondary ERAT",
},
[ POWER9_PME_PM_LSU1_FALSE_LHS ] = {
	.pme_name = "PM_LSU1_FALSE_LHS",
	.pme_code = 0x000000C8A0,
	.pme_short_desc = "False LHS match detected",
	.pme_long_desc = "False LHS match detected",
},
[ POWER9_PME_PM_LSU1_L1_CAM_CANCEL ] = {
	.pme_name = "PM_LSU1_L1_CAM_CANCEL",
	.pme_code = 0x000000F890,
	.pme_short_desc = "ls1 l1 tm cam cancel",
	.pme_long_desc = "ls1 l1 tm cam cancel",
},
[ POWER9_PME_PM_LSU1_LDMX_FIN ] = {
	.pme_name = "PM_LSU1_LDMX_FIN",
	.pme_code = 0x000000D888,
	.pme_short_desc = "New P9 instruction LDMX.",
	.pme_long_desc = "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491):  The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region.  This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]).",
},
[ POWER9_PME_PM_LSU1_SET_MPRED ] = {
	.pme_name = "PM_LSU1_SET_MPRED",
	.pme_code = 0x000000D880,
	.pme_short_desc = "Set prediction(set-p) miss.",
	.pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table",
},
[ POWER9_PME_PM_LSU1_STORE_REJECT ] = {
	.pme_name = "PM_LSU1_STORE_REJECT",
	.pme_code = 0x000000F888,
	.pme_short_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
	.pme_long_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
},
[ POWER9_PME_PM_LSU1_TM_L1_HIT ] = {
	.pme_name = "PM_LSU1_TM_L1_HIT",
	.pme_code = 0x000000E894,
	.pme_short_desc = "Load tm hit in L1",
	.pme_long_desc = "Load tm hit in L1",
},
[ POWER9_PME_PM_LSU1_TM_L1_MISS ] = {
	.pme_name = "PM_LSU1_TM_L1_MISS",
	.pme_code = 0x000000E89C,
	.pme_short_desc = "Load tm L1 miss",
	.pme_long_desc = "Load tm L1 miss",
},
[ POWER9_PME_PM_LSU2_3_LRQF_FULL_CYC ] = {
	.pme_name = "PM_LSU2_3_LRQF_FULL_CYC",
	.pme_code = 0x000000D8BC,
	.pme_short_desc = "Counts the number of cycles the LRQF is full.",
	.pme_long_desc = "Counts the number of cycles the LRQF is full. LRQF is the queue that holds loads between finish and completion. If it fills up, instructions stay in LRQ until completion, potentially backing up the LRQ",
},
[ POWER9_PME_PM_LSU2_ERAT_HIT ] = {
	.pme_name = "PM_LSU2_ERAT_HIT",
	.pme_code = 0x000000E090,
	.pme_short_desc = "Primary ERAT hit.",
	.pme_long_desc = "Primary ERAT hit. There is no secondary ERAT",
},
[ POWER9_PME_PM_LSU2_FALSE_LHS ] = {
	.pme_name = "PM_LSU2_FALSE_LHS",
	.pme_code = 0x000000C0A4,
	.pme_short_desc = "False LHS match detected",
	.pme_long_desc = "False LHS match detected",
},
[ POWER9_PME_PM_LSU2_L1_CAM_CANCEL ] = {
	.pme_name = "PM_LSU2_L1_CAM_CANCEL",
	.pme_code = 0x000000F094,
	.pme_short_desc = "ls2 l1 tm cam cancel",
	.pme_long_desc = "ls2 l1 tm cam cancel",
},
[ POWER9_PME_PM_LSU2_LDMX_FIN ] = {
	.pme_name = "PM_LSU2_LDMX_FIN",
	.pme_code = 0x000000D08C,
	.pme_short_desc = "New P9 instruction LDMX.",
	.pme_long_desc = "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491):  The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region.  This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]).",
},
[ POWER9_PME_PM_LSU2_SET_MPRED ] = {
	.pme_name = "PM_LSU2_SET_MPRED",
	.pme_code = 0x000000D084,
	.pme_short_desc = "Set prediction(set-p) miss.",
	.pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table",
},
[ POWER9_PME_PM_LSU2_STORE_REJECT ] = {
	.pme_name = "PM_LSU2_STORE_REJECT",
	.pme_code = 0x000000F08C,
	.pme_short_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
	.pme_long_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
},
[ POWER9_PME_PM_LSU2_TM_L1_HIT ] = {
	.pme_name = "PM_LSU2_TM_L1_HIT",
	.pme_code = 0x000000E098,
	.pme_short_desc = "Load tm hit in L1",
	.pme_long_desc = "Load tm hit in L1",
},
[ POWER9_PME_PM_LSU2_TM_L1_MISS ] = {
	.pme_name = "PM_LSU2_TM_L1_MISS",
	.pme_code = 0x000000E0A0,
	.pme_short_desc = "Load tm L1 miss",
	.pme_long_desc = "Load tm L1 miss",
},
[ POWER9_PME_PM_LSU3_ERAT_HIT ] = {
	.pme_name = "PM_LSU3_ERAT_HIT",
	.pme_code = 0x000000E890,
	.pme_short_desc = "Primary ERAT hit.",
	.pme_long_desc = "Primary ERAT hit. There is no secondary ERAT",
},
[ POWER9_PME_PM_LSU3_FALSE_LHS ] = {
	.pme_name = "PM_LSU3_FALSE_LHS",
	.pme_code = 0x000000C8A4,
	.pme_short_desc = "False LHS match detected",
	.pme_long_desc = "False LHS match detected",
},
[ POWER9_PME_PM_LSU3_L1_CAM_CANCEL ] = {
	.pme_name = "PM_LSU3_L1_CAM_CANCEL",
	.pme_code = 0x000000F894,
	.pme_short_desc = "ls3 l1 tm cam cancel",
	.pme_long_desc = "ls3 l1 tm cam cancel",
},
[ POWER9_PME_PM_LSU3_LDMX_FIN ] = {
	.pme_name = "PM_LSU3_LDMX_FIN",
	.pme_code = 0x000000D88C,
	.pme_short_desc = "New P9 instruction LDMX.",
	.pme_long_desc = "New P9 instruction LDMX. The definition of this new PMU event is (from the ldmx RFC02491):  The thread has executed an ldmx instruction that accessed a doubleword that contains an effective address within an enabled section of the Load Monitored region.  This event, therefore, should not occur if the FSCR has disabled the load monitored facility (FSCR[52]) or disabled the EBB facility (FSCR[56]).",
},
[ POWER9_PME_PM_LSU3_SET_MPRED ] = {
	.pme_name = "PM_LSU3_SET_MPRED",
	.pme_code = 0x000000D884,
	.pme_short_desc = "Set prediction(set-p) miss.",
	.pme_long_desc = "Set prediction(set-p) miss. The entry was not found in the Set prediction table",
},
[ POWER9_PME_PM_LSU3_STORE_REJECT ] = {
	.pme_name = "PM_LSU3_STORE_REJECT",
	.pme_code = 0x000000F88C,
	.pme_short_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
	.pme_long_desc = "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met",
},
[ POWER9_PME_PM_LSU3_TM_L1_HIT ] = {
	.pme_name = "PM_LSU3_TM_L1_HIT",
	.pme_code = 0x000000E898,
	.pme_short_desc = "Load tm hit in L1",
	.pme_long_desc = "Load tm hit in L1",
},
[ POWER9_PME_PM_LSU3_TM_L1_MISS ] = {
	.pme_name = "PM_LSU3_TM_L1_MISS",
	.pme_code = 0x000000E8A0,
	.pme_short_desc = "Load tm L1 miss",
	.pme_long_desc = "Load tm L1 miss",
},
[ POWER9_PME_PM_LSU_DERAT_MISS ] = {
	.pme_name = "PM_LSU_DERAT_MISS",
	.pme_code = 0x00000200F6,
	.pme_short_desc = "DERAT Reloaded due to a DERAT miss",
	.pme_long_desc = "DERAT Reloaded due to a DERAT miss",
},
[ POWER9_PME_PM_LSU_FIN ] = {
	.pme_name = "PM_LSU_FIN",
	.pme_code = 0x0000030066,
	.pme_short_desc = "LSU Finished a PPC instruction (up to 4 per cycle)",
	.pme_long_desc = "LSU Finished a PPC instruction (up to 4 per cycle)",
},
[ POWER9_PME_PM_LSU_FLUSH_ATOMIC ] = {
	.pme_name = "PM_LSU_FLUSH_ATOMIC",
	.pme_code = 0x000000C8A8,
	.pme_short_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices.",
	.pme_long_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed",
},
[ POWER9_PME_PM_LSU_FLUSH_CI ] = {
	.pme_name = "PM_LSU_FLUSH_CI",
	.pme_code = 0x000000C0A8,
	.pme_short_desc = "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited",
	.pme_long_desc = "Load was not issued to LSU as a cache inhibited (non-cacheable) load but it was later determined to be cache inhibited",
},
[ POWER9_PME_PM_LSU_FLUSH_EMSH ] = {
	.pme_name = "PM_LSU_FLUSH_EMSH",
	.pme_code = 0x000000C0AC,
	.pme_short_desc = "An ERAT miss was detected after a set-p hit.",
	.pme_long_desc = "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address",
},
[ POWER9_PME_PM_LSU_FLUSH_LARX_STCX ] = {
	.pme_name = "PM_LSU_FLUSH_LARX_STCX",
	.pme_code = 0x000000C8B8,
	.pme_short_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread.",
	.pme_long_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches",
},
[ POWER9_PME_PM_LSU_FLUSH_LHL_SHL ] = {
	.pme_name = "PM_LSU_FLUSH_LHL_SHL",
	.pme_code = 0x000000C8B4,
	.pme_short_desc = "The instruction was flushed because of a sequential load/store consistency.",
	.pme_long_desc = "The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores).",
},
[ POWER9_PME_PM_LSU_FLUSH_LHS ] = {
	.pme_name = "PM_LSU_FLUSH_LHS",
	.pme_code = 0x000000C8B0,
	.pme_short_desc = "Effective Address alias flush : no EA match but Real Address match.",
	.pme_long_desc = "Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed",
},
[ POWER9_PME_PM_LSU_FLUSH_NEXT ] = {
	.pme_name = "PM_LSU_FLUSH_NEXT",
	.pme_code = 0x00000020B0,
	.pme_short_desc = "LSU flush next reported at flush time.",
	.pme_long_desc = "LSU flush next reported at flush time. Sometimes these also come with an exception",
},
[ POWER9_PME_PM_LSU_FLUSH_OTHER ] = {
	.pme_name = "PM_LSU_FLUSH_OTHER",
	.pme_code = 0x000000C0BC,
	.pme_short_desc = "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason).",
	.pme_long_desc = "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason). Already gave dval but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops)",
},
[ POWER9_PME_PM_LSU_FLUSH_RELAUNCH_MISS ] = {
	.pme_name = "PM_LSU_FLUSH_RELAUNCH_MISS",
	.pme_code = 0x000000C8AC,
	.pme_short_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent",
	.pme_long_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent",
},
[ POWER9_PME_PM_LSU_FLUSH_SAO ] = {
	.pme_name = "PM_LSU_FLUSH_SAO",
	.pme_code = 0x000000C0B8,
	.pme_short_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush",
	.pme_long_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush",
},
[ POWER9_PME_PM_LSU_FLUSH_UE ] = {
	.pme_name = "PM_LSU_FLUSH_UE",
	.pme_code = 0x000000C0B0,
	.pme_short_desc = "Correctable ECC error on reload data, reported at critical data forward time",
	.pme_long_desc = "Correctable ECC error on reload data, reported at critical data forward time",
},
[ POWER9_PME_PM_LSU_FLUSH_WRK_ARND ] = {
	.pme_name = "PM_LSU_FLUSH_WRK_ARND",
	.pme_code = 0x000000C0B4,
	.pme_short_desc = "LSU workaround flush.",
	.pme_long_desc = "LSU workaround flush. These flushes are setup with programmable scan only latches to perform various actions when the flush macro receives a trigger from the dbg macros. These actions include things like flushing the next op encountered for a particular thread or flushing the next op that is NTC op that is encountered on a particular slice. The kind of flush that the workaround is setup to perform is highly variable.",
},
[ POWER9_PME_PM_LSU_LMQ_FULL_CYC ] = {
	.pme_name = "PM_LSU_LMQ_FULL_CYC",
	.pme_code = 0x000000D0B8,
	.pme_short_desc = "Counts the number of cycles the LMQ is full",
	.pme_long_desc = "Counts the number of cycles the LMQ is full",
},
[ POWER9_PME_PM_LSU_LMQ_SRQ_EMPTY_CYC ] = {
	.pme_name = "PM_LSU_LMQ_SRQ_EMPTY_CYC",
	.pme_code = 0x000002003E,
	.pme_short_desc = "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)",
	.pme_long_desc = "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)",
},
[ POWER9_PME_PM_LSU_NCST ] = {
	.pme_name = "PM_LSU_NCST",
	.pme_code = 0x000000C890,
	.pme_short_desc = "Asserts when a i=1 store op is sent to the nest.",
	.pme_long_desc = "Asserts when a i=1 store op is sent to the nest. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need separate LS0 and LS1",
},
[ POWER9_PME_PM_LSU_REJECT_ERAT_MISS ] = {
	.pme_name = "PM_LSU_REJECT_ERAT_MISS",
	.pme_code = 0x000002E05C,
	.pme_short_desc = "LSU Reject due to ERAT (up to 4 per cycles)",
	.pme_long_desc = "LSU Reject due to ERAT (up to 4 per cycles)",
},
[ POWER9_PME_PM_LSU_REJECT_LHS ] = {
	.pme_name = "PM_LSU_REJECT_LHS",
	.pme_code = 0x000004E05C,
	.pme_short_desc = "LSU Reject due to LHS (up to 4 per cycle)",
	.pme_long_desc = "LSU Reject due to LHS (up to 4 per cycle)",
},
[ POWER9_PME_PM_LSU_REJECT_LMQ_FULL ] = {
	.pme_name = "PM_LSU_REJECT_LMQ_FULL",
	.pme_code = 0x000003001C,
	.pme_short_desc = "LSU Reject due to LMQ full (up to 4 per cycles)",
	.pme_long_desc = "LSU Reject due to LMQ full (up to 4 per cycles)",
},
[ POWER9_PME_PM_LSU_SRQ_FULL_CYC ] = {
	.pme_name = "PM_LSU_SRQ_FULL_CYC",
	.pme_code = 0x000001001A,
	.pme_short_desc = "Cycles in which the Store Queue is full on all 4 slices.",
	.pme_long_desc = "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource",
},
[ POWER9_PME_PM_LSU_STCX_FAIL ] = {
	.pme_name = "PM_LSU_STCX_FAIL",
	.pme_code = 0x000000F080,
	.pme_short_desc = "",
	.pme_long_desc = "",
},
[ POWER9_PME_PM_LSU_STCX ] = {
	.pme_name = "PM_LSU_STCX",
	.pme_code = 0x000000C090,
	.pme_short_desc = "STCX sent to nest, i.",
	.pme_long_desc = "STCX sent to nest, i.e. total",
},
[ POWER9_PME_PM_LWSYNC ] = {
	.pme_name = "PM_LWSYNC",
	.pme_code = 0x0000005894,
	.pme_short_desc = "Lwsync instruction decoded and transferred",
	.pme_long_desc = "Lwsync instruction decoded and transferred",
},
[ POWER9_PME_PM_MATH_FLOP_CMPL ] = {
	.pme_name = "PM_MATH_FLOP_CMPL",
	.pme_code = 0x000004505C,
	.pme_short_desc = "Math flop instruction completed",
	.pme_long_desc = "Math flop instruction completed",
},
[ POWER9_PME_PM_MEM_CO ] = {
	.pme_name = "PM_MEM_CO",
	.pme_code = 0x000004C058,
	.pme_short_desc = "Memory castouts from this thread",
	.pme_long_desc = "Memory castouts from this thread",
},
[ POWER9_PME_PM_MEM_LOC_THRESH_IFU ] = {
	.pme_name = "PM_MEM_LOC_THRESH_IFU",
	.pme_code = 0x0000010058,
	.pme_short_desc = "Local Memory above threshold for IFU speculation control",
	.pme_long_desc = "Local Memory above threshold for IFU speculation control",
},
[ POWER9_PME_PM_MEM_LOC_THRESH_LSU_HIGH ] = {
	.pme_name = "PM_MEM_LOC_THRESH_LSU_HIGH",
	.pme_code = 0x0000040056,
	.pme_short_desc = "Local memory above threshold for LSU medium",
	.pme_long_desc = "Local memory above threshold for LSU medium",
},
[ POWER9_PME_PM_MEM_LOC_THRESH_LSU_MED ] = {
	.pme_name = "PM_MEM_LOC_THRESH_LSU_MED",
	.pme_code = 0x000001C05E,
	.pme_short_desc = "Local memory above threshold for data prefetch",
	.pme_long_desc = "Local memory above threshold for data prefetch",
},
[ POWER9_PME_PM_MEM_PREF ] = {
	.pme_name = "PM_MEM_PREF",
	.pme_code = 0x000002C058,
	.pme_short_desc = "Memory prefetch for this thread.",
	.pme_long_desc = "Memory prefetch for this thread. Includes L4",
},
[ POWER9_PME_PM_MEM_READ ] = {
	.pme_name = "PM_MEM_READ",
	.pme_code = 0x0000010056,
	.pme_short_desc = "Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch).",
	.pme_long_desc = "Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4",
},
[ POWER9_PME_PM_MEM_RWITM ] = {
	.pme_name = "PM_MEM_RWITM",
	.pme_code = 0x000003C05E,
	.pme_short_desc = "Memory Read With Intent to Modify for this thread",
	.pme_long_desc = "Memory Read With Intent to Modify for this thread",
},
[ POWER9_PME_PM_MRK_BACK_BR_CMPL ] = {
	.pme_name = "PM_MRK_BACK_BR_CMPL",
	.pme_code = 0x000003515E,
	.pme_short_desc = "Marked branch instruction completed with a target address less than current instruction address",
	.pme_long_desc = "Marked branch instruction completed with a target address less than current instruction address",
},
[ POWER9_PME_PM_MRK_BR_2PATH ] = {
	.pme_name = "PM_MRK_BR_2PATH",
	.pme_code = 0x0000010138,
	.pme_short_desc = "marked branches which are not strongly biased",
	.pme_long_desc = "marked branches which are not strongly biased",
},
[ POWER9_PME_PM_MRK_BR_CMPL ] = {
	.pme_name = "PM_MRK_BR_CMPL",
	.pme_code = 0x000001016E,
	.pme_short_desc = "Branch Instruction completed",
	.pme_long_desc = "Branch Instruction completed",
},
[ POWER9_PME_PM_MRK_BR_MPRED_CMPL ] = {
	.pme_name = "PM_MRK_BR_MPRED_CMPL",
	.pme_code = 0x00000301E4,
	.pme_short_desc = "Marked Branch Mispredicted",
	.pme_long_desc = "Marked Branch Mispredicted",
},
[ POWER9_PME_PM_MRK_BR_TAKEN_CMPL ] = {
	.pme_name = "PM_MRK_BR_TAKEN_CMPL",
	.pme_code = 0x00000101E2,
	.pme_short_desc = "Marked Branch Taken completed",
	.pme_long_desc = "Marked Branch Taken completed",
},
[ POWER9_PME_PM_MRK_BRU_FIN ] = {
	.pme_name = "PM_MRK_BRU_FIN",
	.pme_code = 0x000002013A,
	.pme_short_desc = "bru marked instr finish",
	.pme_long_desc = "bru marked instr finish",
},
[ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD_CYC",
	.pme_code = 0x000004D12E,
	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL2L3_MOD",
	.pme_code = 0x000003D14E,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
	.pme_code = 0x000002C128,
	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL2L3_SHR",
	.pme_code = 0x000001D150,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_DL4_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL4_CYC",
	.pme_code = 0x000002C12C,
	.pme_short_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_DL4 ] = {
	.pme_name = "PM_MRK_DATA_FROM_DL4",
	.pme_code = 0x000001D152,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_DMEM_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_DMEM_CYC",
	.pme_code = 0x000004E11E,
	.pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_DMEM ] = {
	.pme_name = "PM_MRK_DATA_FROM_DMEM",
	.pme_code = 0x000003D14C,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L21_MOD_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L21_MOD_CYC",
	.pme_code = 0x000003D148,
	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L21_MOD ] = {
	.pme_name = "PM_MRK_DATA_FROM_L21_MOD",
	.pme_code = 0x000004D146,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L21_SHR_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L21_SHR_CYC",
	.pme_code = 0x000001D154,
	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L21_SHR ] = {
	.pme_name = "PM_MRK_DATA_FROM_L21_SHR",
	.pme_code = 0x000002D14E,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_CYC",
	.pme_code = 0x0000014156,
	.pme_short_desc = "Duration in cycles to reload from local core's L2 due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L2 due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
	.pme_code = 0x000001415A,
	.pme_short_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
	.pme_code = 0x000002D148,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC",
	.pme_code = 0x000003D140,
	.pme_short_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
	.pme_code = 0x000002C124,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_MEPF_CYC",
	.pme_code = 0x000003D144,
	.pme_short_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state.",
	.pme_long_desc = "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2_MEPF ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_MEPF",
	.pme_code = 0x000004C120,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state.",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2MISS_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2MISS_CYC",
	.pme_code = 0x0000035152,
	.pme_short_desc = "Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2MISS ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2MISS",
	.pme_code = 0x00000401E8,
	.pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L2 due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC",
	.pme_code = 0x0000014158,
	.pme_short_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2_NO_CONFLICT",
	.pme_code = 0x000002C120,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L2 ] = {
	.pme_name = "PM_MRK_DATA_FROM_L2",
	.pme_code = 0x000002C126,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L2 due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_MOD_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_ECO_MOD_CYC",
	.pme_code = 0x0000035158,
	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_ECO_MOD",
	.pme_code = 0x000004D144,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_SHR_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC",
	.pme_code = 0x000001D142,
	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_ECO_SHR",
	.pme_code = 0x000002D14C,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L31_MOD_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_MOD_CYC",
	.pme_code = 0x000001D140,
	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L31_MOD ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_MOD",
	.pme_code = 0x000002D144,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L31_SHR_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_SHR_CYC",
	.pme_code = 0x0000035156,
	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L31_SHR ] = {
	.pme_name = "PM_MRK_DATA_FROM_L31_SHR",
	.pme_code = 0x000004D124,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L3_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_CYC",
	.pme_code = 0x0000035154,
	.pme_short_desc = "Duration in cycles to reload from local core's L3 due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L3 due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC",
	.pme_code = 0x000002C122,
	.pme_short_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x000001D144,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_MEPF_CYC",
	.pme_code = 0x000001415C,
	.pme_short_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L3_MEPF ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_MEPF",
	.pme_code = 0x000002D142,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state.",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L3MISS_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3MISS_CYC",
	.pme_code = 0x000001415E,
	.pme_short_desc = "Duration in cycles to reload from a location other than the local core's L3 due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from a location other than the local core's L3 due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L3MISS ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3MISS",
	.pme_code = 0x00000201E4,
	.pme_short_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC",
	.pme_code = 0x000004C124,
	.pme_short_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3_NO_CONFLICT",
	.pme_code = 0x000003D146,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_L3 ] = {
	.pme_name = "PM_MRK_DATA_FROM_L3",
	.pme_code = 0x000004D142,
	.pme_short_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from local core's L3 due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_LL4_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_LL4_CYC",
	.pme_code = 0x000002C12E,
	.pme_short_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_LL4 ] = {
	.pme_name = "PM_MRK_DATA_FROM_LL4",
	.pme_code = 0x000001D14C,
	.pme_short_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_LMEM_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_LMEM_CYC",
	.pme_code = 0x000004D128,
	.pme_short_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from the local chip's Memory due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_LMEM ] = {
	.pme_name = "PM_MRK_DATA_FROM_LMEM",
	.pme_code = 0x000003D142,
	.pme_short_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_MEMORY_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_MEMORY_CYC",
	.pme_code = 0x000001D146,
	.pme_short_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_MEMORY ] = {
	.pme_name = "PM_MRK_DATA_FROM_MEMORY",
	.pme_code = 0x00000201E0,
	.pme_short_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC",
	.pme_code = 0x000001D14E,
	.pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
	.pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_MRK_DATA_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x000002D120,
	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
	.pme_code = 0x000003515A,
	.pme_short_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
	.pme_code = 0x000004D140,
	.pme_short_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
	.pme_code = 0x000002D14A,
	.pme_short_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL2L3_MOD",
	.pme_code = 0x000001D14A,
	.pme_short_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
	.pme_code = 0x000004C12A,
	.pme_short_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
	.pme_long_desc = "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL2L3_SHR",
	.pme_code = 0x0000035150,
	.pme_short_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_RL4_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL4_CYC",
	.pme_code = 0x000004D12A,
	.pme_short_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_RL4 ] = {
	.pme_name = "PM_MRK_DATA_FROM_RL4",
	.pme_code = 0x000003515C,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_RMEM_CYC ] = {
	.pme_name = "PM_MRK_DATA_FROM_RMEM_CYC",
	.pme_code = 0x000002C12A,
	.pme_short_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load",
	.pme_long_desc = "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load",
},
[ POWER9_PME_PM_MRK_DATA_FROM_RMEM ] = {
	.pme_name = "PM_MRK_DATA_FROM_RMEM",
	.pme_code = 0x000001D148,
	.pme_short_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load",
	.pme_long_desc = "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load",
},
[ POWER9_PME_PM_MRK_DCACHE_RELOAD_INTV ] = {
	.pme_name = "PM_MRK_DCACHE_RELOAD_INTV",
	.pme_code = 0x0000040118,
	.pme_short_desc = "Combined Intervention event",
	.pme_long_desc = "Combined Intervention event",
},
[ POWER9_PME_PM_MRK_DERAT_MISS_16G ] = {
	.pme_name = "PM_MRK_DERAT_MISS_16G",
	.pme_code = 0x000004C15C,
	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G",
	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16G",
},
[ POWER9_PME_PM_MRK_DERAT_MISS_16M ] = {
	.pme_name = "PM_MRK_DERAT_MISS_16M",
	.pme_code = 0x000003D154,
	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M",
	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 16M",
},
[ POWER9_PME_PM_MRK_DERAT_MISS_1G ] = {
	.pme_name = "PM_MRK_DERAT_MISS_1G",
	.pme_code = 0x000003D152,
	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 1G.",
	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation",
},
[ POWER9_PME_PM_MRK_DERAT_MISS_2M ] = {
	.pme_name = "PM_MRK_DERAT_MISS_2M",
	.pme_code = 0x000002D152,
	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 2M.",
	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation",
},
[ POWER9_PME_PM_MRK_DERAT_MISS_4K ] = {
	.pme_name = "PM_MRK_DERAT_MISS_4K",
	.pme_code = 0x000002D150,
	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K",
	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 4K",
},
[ POWER9_PME_PM_MRK_DERAT_MISS_64K ] = {
	.pme_name = "PM_MRK_DERAT_MISS_64K",
	.pme_code = 0x000002D154,
	.pme_short_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K",
	.pme_long_desc = "Marked Data ERAT Miss (Data TLB Access) page size 64K",
},
[ POWER9_PME_PM_MRK_DERAT_MISS ] = {
	.pme_name = "PM_MRK_DERAT_MISS",
	.pme_code = 0x00000301E6,
	.pme_short_desc = "Erat Miss (TLB Access) All page sizes",
	.pme_long_desc = "Erat Miss (TLB Access) All page sizes",
},
[ POWER9_PME_PM_MRK_DFU_FIN ] = {
	.pme_name = "PM_MRK_DFU_FIN",
	.pme_code = 0x0000020132,
	.pme_short_desc = "Decimal Unit marked Instruction Finish",
	.pme_long_desc = "Decimal Unit marked Instruction Finish",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_MOD ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_DL2L3_MOD",
	.pme_code = 0x000004F148,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_DL2L3_SHR ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_DL2L3_SHR",
	.pme_code = 0x000003F148,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_DL4 ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_DL4",
	.pme_code = 0x000003F14C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_DMEM ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_DMEM",
	.pme_code = 0x000004F14C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L21_MOD ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L21_MOD",
	.pme_code = 0x000004F146,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L21_SHR ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L21_SHR",
	.pme_code = 0x000003F146,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L2_MEPF ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L2_MEPF",
	.pme_code = 0x000002F140,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L2MISS ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L2MISS",
	.pme_code = 0x000001F14E,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L2_NO_CONFLICT ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
	.pme_code = 0x000001F140,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L2 ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L2",
	.pme_code = 0x000001F142,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L31_ECO_MOD ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L31_ECO_MOD",
	.pme_code = 0x000004F144,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L31_ECO_SHR ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L31_ECO_SHR",
	.pme_code = 0x000003F144,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L31_MOD ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L31_MOD",
	.pme_code = 0x000002F144,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L31_SHR ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L31_SHR",
	.pme_code = 0x000001F146,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
	.pme_code = 0x000003F142,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L3_MEPF ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L3_MEPF",
	.pme_code = 0x000002F142,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L3MISS ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L3MISS",
	.pme_code = 0x000004F14E,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L3_NO_CONFLICT ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT",
	.pme_code = 0x000001F144,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_L3 ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_L3",
	.pme_code = 0x000004F142,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_LL4 ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_LL4",
	.pme_code = 0x000001F14C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_LMEM ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_LMEM",
	.pme_code = 0x000002F148,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_MEMORY ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_MEMORY",
	.pme_code = 0x000002F14C,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
	.pme_code = 0x000004F14A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_ON_CHIP_CACHE ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
	.pme_code = 0x000001F148,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_MOD ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_RL2L3_MOD",
	.pme_code = 0x000002F146,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_RL2L3_SHR ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_RL2L3_SHR",
	.pme_code = 0x000001F14A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_RL4 ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_RL4",
	.pme_code = 0x000002F14A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DPTEG_FROM_RMEM ] = {
	.pme_name = "PM_MRK_DPTEG_FROM_RMEM",
	.pme_code = 0x000003F14A,
	.pme_short_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request.",
	.pme_long_desc = "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
},
[ POWER9_PME_PM_MRK_DTLB_MISS_16G ] = {
	.pme_name = "PM_MRK_DTLB_MISS_16G",
	.pme_code = 0x000002D15E,
	.pme_short_desc = "Marked Data TLB Miss page size 16G",
	.pme_long_desc = "Marked Data TLB Miss page size 16G",
},
[ POWER9_PME_PM_MRK_DTLB_MISS_16M ] = {
	.pme_name = "PM_MRK_DTLB_MISS_16M",
	.pme_code = 0x000004C15E,
	.pme_short_desc = "Marked Data TLB Miss page size 16M",
	.pme_long_desc = "Marked Data TLB Miss page size 16M",
},
[ POWER9_PME_PM_MRK_DTLB_MISS_1G ] = {
	.pme_name = "PM_MRK_DTLB_MISS_1G",
	.pme_code = 0x000001D15C,
	.pme_short_desc = "Marked Data TLB reload (after a miss) page size 2M.",
	.pme_long_desc = "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used",
},
[ POWER9_PME_PM_MRK_DTLB_MISS_4K ] = {
	.pme_name = "PM_MRK_DTLB_MISS_4K",
	.pme_code = 0x000002D156,
	.pme_short_desc = "Marked Data TLB Miss page size 4k",
	.pme_long_desc = "Marked Data TLB Miss page size 4k",
},
[ POWER9_PME_PM_MRK_DTLB_MISS_64K ] = {
	.pme_name = "PM_MRK_DTLB_MISS_64K",
	.pme_code = 0x000003D156,
	.pme_short_desc = "Marked Data TLB Miss page size 64K",
	.pme_long_desc = "Marked Data TLB Miss page size 64K",
},
[ POWER9_PME_PM_MRK_DTLB_MISS ] = {
	.pme_name = "PM_MRK_DTLB_MISS",
	.pme_code = 0x00000401E4,
	.pme_short_desc = "Marked dtlb miss",
	.pme_long_desc = "Marked dtlb miss",
},
[ POWER9_PME_PM_MRK_FAB_RSP_BKILL_CYC ] = {
	.pme_name = "PM_MRK_FAB_RSP_BKILL_CYC",
	.pme_code = 0x000001F152,
	.pme_short_desc = "cycles L2 RC took for a bkill",
	.pme_long_desc = "cycles L2 RC took for a bkill",
},
[ POWER9_PME_PM_MRK_FAB_RSP_BKILL ] = {
	.pme_name = "PM_MRK_FAB_RSP_BKILL",
	.pme_code = 0x0000040154,
	.pme_short_desc = "Marked store had to do a bkill",
	.pme_long_desc = "Marked store had to do a bkill",
},
[ POWER9_PME_PM_MRK_FAB_RSP_CLAIM_RTY ] = {
	.pme_name = "PM_MRK_FAB_RSP_CLAIM_RTY",
	.pme_code = 0x000003015E,
	.pme_short_desc = "Sampled store did a rwitm and got a rty",
	.pme_long_desc = "Sampled store did a rwitm and got a rty",
},
[ POWER9_PME_PM_MRK_FAB_RSP_DCLAIM_CYC ] = {
	.pme_name = "PM_MRK_FAB_RSP_DCLAIM_CYC",
	.pme_code = 0x000002F152,
	.pme_short_desc = "cycles L2 RC took for a dclaim",
	.pme_long_desc = "cycles L2 RC took for a dclaim",
},
[ POWER9_PME_PM_MRK_FAB_RSP_DCLAIM ] = {
	.pme_name = "PM_MRK_FAB_RSP_DCLAIM",
	.pme_code = 0x0000030154,
	.pme_short_desc = "Marked store had to do a dclaim",
	.pme_long_desc = "Marked store had to do a dclaim",
},
[ POWER9_PME_PM_MRK_FAB_RSP_RD_RTY ] = {
	.pme_name = "PM_MRK_FAB_RSP_RD_RTY",
	.pme_code = 0x000004015E,
	.pme_short_desc = "Sampled L2 reads retry count",
	.pme_long_desc = "Sampled L2 reads retry count",
},
[ POWER9_PME_PM_MRK_FAB_RSP_RD_T_INTV ] = {
	.pme_name = "PM_MRK_FAB_RSP_RD_T_INTV",
	.pme_code = 0x000001015E,
	.pme_short_desc = "Sampled Read got a T intervention",
	.pme_long_desc = "Sampled Read got a T intervention",
},
[ POWER9_PME_PM_MRK_FAB_RSP_RWITM_CYC ] = {
	.pme_name = "PM_MRK_FAB_RSP_RWITM_CYC",
	.pme_code = 0x000004F150,
	.pme_short_desc = "cycles L2 RC took for a rwitm",
	.pme_long_desc = "cycles L2 RC took for a rwitm",
},
[ POWER9_PME_PM_MRK_FAB_RSP_RWITM_RTY ] = {
	.pme_name = "PM_MRK_FAB_RSP_RWITM_RTY",
	.pme_code = 0x000002015E,
	.pme_short_desc = "Sampled store did a rwitm and got a rty",
	.pme_long_desc = "Sampled store did a rwitm and got a rty",
},
[ POWER9_PME_PM_MRK_FXU_FIN ] = {
	.pme_name = "PM_MRK_FXU_FIN",
	.pme_code = 0x0000020134,
	.pme_short_desc = "fxu marked instr finish",
	.pme_long_desc = "fxu marked instr finish",
},
[ POWER9_PME_PM_MRK_IC_MISS ] = {
	.pme_name = "PM_MRK_IC_MISS",
	.pme_code = 0x000004013A,
	.pme_short_desc = "Marked instruction experienced I cache miss",
	.pme_long_desc = "Marked instruction experienced I cache miss",
},
[ POWER9_PME_PM_MRK_INST_CMPL ] = {
	.pme_name = "PM_MRK_INST_CMPL",
	.pme_code = 0x00000401E0,
	.pme_short_desc = "marked instruction completed",
	.pme_long_desc = "marked instruction completed",
},
[ POWER9_PME_PM_MRK_INST_DECODED ] = {
	.pme_name = "PM_MRK_INST_DECODED",
	.pme_code = 0x0000020130,
	.pme_short_desc = "An instruction was marked at decode time.",
	.pme_long_desc = "An instruction was marked at decode time. Random Instruction Sampling (RIS) only",
},
[ POWER9_PME_PM_MRK_INST_DISP ] = {
	.pme_name = "PM_MRK_INST_DISP",
	.pme_code = 0x00000101E0,
	.pme_short_desc = "The thread has dispatched a randomly sampled marked instruction",
	.pme_long_desc = "The thread has dispatched a randomly sampled marked instruction",
},
[ POWER9_PME_PM_MRK_INST_FIN ] = {
	.pme_name = "PM_MRK_INST_FIN",
	.pme_code = 0x0000030130,
	.pme_short_desc = "marked instruction finished",
	.pme_long_desc = "marked instruction finished",
},
[ POWER9_PME_PM_MRK_INST_FROM_L3MISS ] = {
	.pme_name = "PM_MRK_INST_FROM_L3MISS",
	.pme_code = 0x00000401E6,
	.pme_short_desc = "Marked instruction was reloaded from a location beyond the local chiplet",
	.pme_long_desc = "Marked instruction was reloaded from a location beyond the local chiplet",
},
[ POWER9_PME_PM_MRK_INST_ISSUED ] = {
	.pme_name = "PM_MRK_INST_ISSUED",
	.pme_code = 0x0000010132,
	.pme_short_desc = "Marked instruction issued",
	.pme_long_desc = "Marked instruction issued",
},
[ POWER9_PME_PM_MRK_INST_TIMEO ] = {
	.pme_name = "PM_MRK_INST_TIMEO",
	.pme_code = 0x0000040134,
	.pme_short_desc = "marked Instruction finish timeout (instruction lost)",
	.pme_long_desc = "marked Instruction finish timeout (instruction lost)",
},
[ POWER9_PME_PM_MRK_INST ] = {
	.pme_name = "PM_MRK_INST",
	.pme_code = 0x0000024058,
	.pme_short_desc = "An instruction was marked.",
	.pme_long_desc = "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens",
},
[ POWER9_PME_PM_MRK_L1_ICACHE_MISS ] = {
	.pme_name = "PM_MRK_L1_ICACHE_MISS",
	.pme_code = 0x00000101E4,
	.pme_short_desc = "sampled Instruction suffered an icache Miss",
	.pme_long_desc = "sampled Instruction suffered an icache Miss",
},
[ POWER9_PME_PM_MRK_L1_RELOAD_VALID ] = {
	.pme_name = "PM_MRK_L1_RELOAD_VALID",
	.pme_code = 0x00000101EA,
	.pme_short_desc = "Marked demand reload",
	.pme_long_desc = "Marked demand reload",
},
[ POWER9_PME_PM_MRK_L2_RC_DISP ] = {
	.pme_name = "PM_MRK_L2_RC_DISP",
	.pme_code = 0x0000020114,
	.pme_short_desc = "Marked Instruction RC dispatched in L2",
	.pme_long_desc = "Marked Instruction RC dispatched in L2",
},
[ POWER9_PME_PM_MRK_L2_RC_DONE ] = {
	.pme_name = "PM_MRK_L2_RC_DONE",
	.pme_code = 0x000003012A,
	.pme_short_desc = "Marked RC done",
	.pme_long_desc = "Marked RC done",
},
[ POWER9_PME_PM_MRK_L2_TM_REQ_ABORT ] = {
	.pme_name = "PM_MRK_L2_TM_REQ_ABORT",
	.pme_code = 0x000001E15E,
	.pme_short_desc = "TM abort",
	.pme_long_desc = "TM abort",
},
[ POWER9_PME_PM_MRK_L2_TM_ST_ABORT_SISTER ] = {
	.pme_name = "PM_MRK_L2_TM_ST_ABORT_SISTER",
	.pme_code = 0x000003E15C,
	.pme_short_desc = "TM marked store abort for this thread",
	.pme_long_desc = "TM marked store abort for this thread",
},
[ POWER9_PME_PM_MRK_LARX_FIN ] = {
	.pme_name = "PM_MRK_LARX_FIN",
	.pme_code = 0x0000040116,
	.pme_short_desc = "Larx finished",
	.pme_long_desc = "Larx finished",
},
[ POWER9_PME_PM_MRK_LD_MISS_EXPOSED_CYC ] = {
	.pme_name = "PM_MRK_LD_MISS_EXPOSED_CYC",
	.pme_code = 0x000001013E,
	.pme_short_desc = "Marked Load exposed Miss (use edge detect to count #)",
	.pme_long_desc = "Marked Load exposed Miss (use edge detect to count #)",
},
[ POWER9_PME_PM_MRK_LD_MISS_L1_CYC ] = {
	.pme_name = "PM_MRK_LD_MISS_L1_CYC",
	.pme_code = 0x000001D056,
	.pme_short_desc = "Marked ld latency",
	.pme_long_desc = "Marked ld latency",
},
[ POWER9_PME_PM_MRK_LD_MISS_L1 ] = {
	.pme_name = "PM_MRK_LD_MISS_L1",
	.pme_code = 0x00000201E2,
	.pme_short_desc = "Marked DL1 Demand Miss counted at exec time.",
	.pme_long_desc = "Marked DL1 Demand Miss counted at exec time. Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.",
},
[ POWER9_PME_PM_MRK_LSU_DERAT_MISS ] = {
	.pme_name = "PM_MRK_LSU_DERAT_MISS",
	.pme_code = 0x0000030162,
	.pme_short_desc = "Marked derat reload (miss) for any page size",
	.pme_long_desc = "Marked derat reload (miss) for any page size",
},
[ POWER9_PME_PM_MRK_LSU_FIN ] = {
	.pme_name = "PM_MRK_LSU_FIN",
	.pme_code = 0x0000040132,
	.pme_short_desc = "lsu marked instr PPC finish",
	.pme_long_desc = "lsu marked instr PPC finish",
},
[ POWER9_PME_PM_MRK_LSU_FLUSH_ATOMIC ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_ATOMIC",
	.pme_code = 0x000000D098,
	.pme_short_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices.",
	.pme_long_desc = "Quad-word loads (lq) are considered atomic because they always span at least 2 slices. If a snoop or store from another thread changes the data the load is accessing between the 2 or 3 pieces of the lq instruction, the lq will be flushed",
},
[ POWER9_PME_PM_MRK_LSU_FLUSH_EMSH ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_EMSH",
	.pme_code = 0x000000D898,
	.pme_short_desc = "An ERAT miss was detected after a set-p hit.",
	.pme_long_desc = "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the instruction gets flushed because the instruction was working on the wrong address",
},
[ POWER9_PME_PM_MRK_LSU_FLUSH_LARX_STCX ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_LARX_STCX",
	.pme_code = 0x000000D8A4,
	.pme_short_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread.",
	.pme_long_desc = "A larx is flushed because an older larx has an LMQ reservation for the same thread. A stcx is flushed because an older stcx is in the LMQ. The flush happens when the older larx/stcx relaunches",
},
[ POWER9_PME_PM_MRK_LSU_FLUSH_LHL_SHL ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_LHL_SHL",
	.pme_code = 0x000000D8A0,
	.pme_short_desc = "The instruction was flushed because of a sequential load/store consistency.",
	.pme_long_desc = "The instruction was flushed because of a sequential load/store consistency. If a load or store hits on an older load that has either been snooped (for loads) or has stale data (for stores).",
},
[ POWER9_PME_PM_MRK_LSU_FLUSH_LHS ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_LHS",
	.pme_code = 0x000000D0A0,
	.pme_short_desc = "Effective Address alias flush : no EA match but Real Address match.",
	.pme_long_desc = "Effective Address alias flush : no EA match but Real Address match. If the data has not yet been returned for this load, the instruction will just be rejected, but if it has returned data, it will be flushed",
},
[ POWER9_PME_PM_MRK_LSU_FLUSH_RELAUNCH_MISS ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_RELAUNCH_MISS",
	.pme_code = 0x000000D09C,
	.pme_short_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent",
	.pme_long_desc = "If a load that has already returned data and has to relaunch for any reason then gets a miss (erat, setp, data cache), it will often be flushed at relaunch time because the data might be inconsistent",
},
[ POWER9_PME_PM_MRK_LSU_FLUSH_SAO ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_SAO",
	.pme_code = 0x000000D0A4,
	.pme_short_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush",
	.pme_long_desc = "A load-hit-load condition with Strong Address Ordering will have address compare disabled and flush",
},
[ POWER9_PME_PM_MRK_LSU_FLUSH_UE ] = {
	.pme_name = "PM_MRK_LSU_FLUSH_UE",
	.pme_code = 0x000000D89C,
	.pme_short_desc = "Correctable ECC error on reload data, reported at critical data forward time",
	.pme_long_desc = "Correctable ECC error on reload data, reported at critical data forward time",
},
[ POWER9_PME_PM_MRK_NTC_CYC ] = {
	.pme_name = "PM_MRK_NTC_CYC",
	.pme_code = 0x000002011C,
	.pme_short_desc = "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)",
	.pme_long_desc = "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)",
},
[ POWER9_PME_PM_MRK_NTF_FIN ] = {
	.pme_name = "PM_MRK_NTF_FIN",
	.pme_code = 0x0000020112,
	.pme_short_desc = "Marked next to finish instruction finished",
	.pme_long_desc = "Marked next to finish instruction finished",
},
[ POWER9_PME_PM_MRK_PROBE_NOP_CMPL ] = {
	.pme_name = "PM_MRK_PROBE_NOP_CMPL",
	.pme_code = 0x000001F05E,
	.pme_short_desc = "Marked probeNops completed",
	.pme_long_desc = "Marked probeNops completed",
},
[ POWER9_PME_PM_MRK_RUN_CYC ] = {
	.pme_name = "PM_MRK_RUN_CYC",
	.pme_code = 0x000001D15E,
	.pme_short_desc = "Run cycles in which a marked instruction is in the pipeline",
	.pme_long_desc = "Run cycles in which a marked instruction is in the pipeline",
},
[ POWER9_PME_PM_MRK_STALL_CMPLU_CYC ] = {
	.pme_name = "PM_MRK_STALL_CMPLU_CYC",
	.pme_code = 0x000003013E,
	.pme_short_desc = "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)",
	.pme_long_desc = "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)",
},
[ POWER9_PME_PM_MRK_ST_CMPL_INT ] = {
	.pme_name = "PM_MRK_ST_CMPL_INT",
	.pme_code = 0x0000030134,
	.pme_short_desc = "marked store finished with intervention",
	.pme_long_desc = "marked store finished with intervention",
},
[ POWER9_PME_PM_MRK_ST_CMPL ] = {
	.pme_name = "PM_MRK_ST_CMPL",
	.pme_code = 0x00000301E2,
	.pme_short_desc = "Marked store completed and sent to nest",
	.pme_long_desc = "Marked store completed and sent to nest",
},
[ POWER9_PME_PM_MRK_STCX_FAIL ] = {
	.pme_name = "PM_MRK_STCX_FAIL",
	.pme_code = 0x000003E158,
	.pme_short_desc = "marked stcx failed",
	.pme_long_desc = "marked stcx failed",
},
[ POWER9_PME_PM_MRK_STCX_FIN ] = {
	.pme_name = "PM_MRK_STCX_FIN",
	.pme_code = 0x0000024056,
	.pme_short_desc = "Number of marked stcx instructions finished.",
	.pme_long_desc = "Number of marked stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed",
},
[ POWER9_PME_PM_MRK_ST_DONE_L2 ] = {
	.pme_name = "PM_MRK_ST_DONE_L2",
	.pme_code = 0x0000010134,
	.pme_short_desc = "marked store completed in L2 ( RC machine done)",
	.pme_long_desc = "marked store completed in L2 ( RC machine done)",
},
[ POWER9_PME_PM_MRK_ST_DRAIN_TO_L2DISP_CYC ] = {
	.pme_name = "PM_MRK_ST_DRAIN_TO_L2DISP_CYC",
	.pme_code = 0x000003F150,
	.pme_short_desc = "cycles to drain st from core to L2",
	.pme_long_desc = "cycles to drain st from core to L2",
},
[ POWER9_PME_PM_MRK_ST_FWD ] = {
	.pme_name = "PM_MRK_ST_FWD",
	.pme_code = 0x000003012C,
	.pme_short_desc = "Marked st forwards",
	.pme_long_desc = "Marked st forwards",
},
[ POWER9_PME_PM_MRK_ST_L2DISP_TO_CMPL_CYC ] = {
	.pme_name = "PM_MRK_ST_L2DISP_TO_CMPL_CYC",
	.pme_code = 0x000001F150,
	.pme_short_desc = "cycles from L2 rc disp to l2 rc completion",
	.pme_long_desc = "cycles from L2 rc disp to l2 rc completion",
},
[ POWER9_PME_PM_MRK_ST_NEST ] = {
	.pme_name = "PM_MRK_ST_NEST",
	.pme_code = 0x0000020138,
	.pme_short_desc = "Marked store sent to nest",
	.pme_long_desc = "Marked store sent to nest",
},
[ POWER9_PME_PM_MRK_TEND_FAIL ] = {
	.pme_name = "PM_MRK_TEND_FAIL",
	.pme_code = 0x00000028A4,
	.pme_short_desc = "Nested or not nested tend failed for a marked tend instruction",
	.pme_long_desc = "Nested or not nested tend failed for a marked tend instruction",
},
[ POWER9_PME_PM_MRK_VSU_FIN ] = {
	.pme_name = "PM_MRK_VSU_FIN",
	.pme_code = 0x0000030132,
	.pme_short_desc = "VSU marked instr finish",
	.pme_long_desc = "VSU marked instr finish",
},
[ POWER9_PME_PM_MULT_MRK ] = {
	.pme_name = "PM_MULT_MRK",
	.pme_code = 0x000003D15E,
	.pme_short_desc = "mult marked instr",
	.pme_long_desc = "mult marked instr",
},
[ POWER9_PME_PM_NEST_REF_CLK ] = {
	.pme_name = "PM_NEST_REF_CLK",
	.pme_code = 0x000003006E,
	.pme_short_desc = "Multiply by 4 to obtain the number of PB cycles",
	.pme_long_desc = "Multiply by 4 to obtain the number of PB cycles",
},
[ POWER9_PME_PM_NON_DATA_STORE ] = {
	.pme_name = "PM_NON_DATA_STORE",
	.pme_code = 0x000000F8A0,
	.pme_short_desc = "All ops that drain from s2q to L2 and contain no data",
	.pme_long_desc = "All ops that drain from s2q to L2 and contain no data",
},
[ POWER9_PME_PM_NON_FMA_FLOP_CMPL ] = {
	.pme_name = "PM_NON_FMA_FLOP_CMPL",
	.pme_code = 0x000004D056,
	.pme_short_desc = "Non FMA instruction completed",
	.pme_long_desc = "Non FMA instruction completed",
},
[ POWER9_PME_PM_NON_MATH_FLOP_CMPL ] = {
	.pme_name = "PM_NON_MATH_FLOP_CMPL",
	.pme_code = 0x000004D05A,
	.pme_short_desc = "Non FLOP operation completed",
	.pme_long_desc = "Non FLOP operation completed",
},
[ POWER9_PME_PM_NON_TM_RST_SC ] = {
	.pme_name = "PM_NON_TM_RST_SC",
	.pme_code = 0x00000260A6,
	.pme_short_desc = "Non-TM snp rst TM SC",
	.pme_long_desc = "Non-TM snp rst TM SC",
},
[ POWER9_PME_PM_NTC_ALL_FIN ] = {
	.pme_name = "PM_NTC_ALL_FIN",
	.pme_code = 0x000002001A,
	.pme_short_desc = "Cycles after all instructions have finished to group completed",
	.pme_long_desc = "Cycles after all instructions have finished to group completed",
},
[ POWER9_PME_PM_NTC_FIN ] = {
	.pme_name = "PM_NTC_FIN",
	.pme_code = 0x000002405A,
	.pme_short_desc = "Cycles in which the oldest instruction in the pipeline (NTC) finishes.",
	.pme_long_desc = "Cycles in which the oldest instruction in the pipeline (NTC) finishes. This event is used to account for cycles in which work is being completed in the CPI stack",
},
[ POWER9_PME_PM_NTC_ISSUE_HELD_ARB ] = {
	.pme_name = "PM_NTC_ISSUE_HELD_ARB",
	.pme_code = 0x000002E016,
	.pme_short_desc = "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)",
	.pme_long_desc = "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)",
},
[ POWER9_PME_PM_NTC_ISSUE_HELD_DARQ_FULL ] = {
	.pme_name = "PM_NTC_ISSUE_HELD_DARQ_FULL",
	.pme_code = 0x000001006A,
	.pme_short_desc = "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it",
	.pme_long_desc = "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it",
},
[ POWER9_PME_PM_NTC_ISSUE_HELD_OTHER ] = {
	.pme_name = "PM_NTC_ISSUE_HELD_OTHER",
	.pme_code = 0x000003D05A,
	.pme_short_desc = "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU",
	.pme_long_desc = "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU",
},
[ POWER9_PME_PM_PARTIAL_ST_FIN ] = {
	.pme_name = "PM_PARTIAL_ST_FIN",
	.pme_code = 0x0000034054,
	.pme_short_desc = "Any store finished by an LSU slice",
	.pme_long_desc = "Any store finished by an LSU slice",
},
[ POWER9_PME_PM_PMC1_OVERFLOW ] = {
	.pme_name = "PM_PMC1_OVERFLOW",
	.pme_code = 0x0000020010,
	.pme_short_desc = "Overflow from counter 1",
	.pme_long_desc = "Overflow from counter 1",
},
[ POWER9_PME_PM_PMC1_REWIND ] = {
	.pme_name = "PM_PMC1_REWIND",
	.pme_code = 0x000004D02C,
	.pme_short_desc = "",
	.pme_long_desc = "",
},
[ POWER9_PME_PM_PMC1_SAVED ] = {
	.pme_name = "PM_PMC1_SAVED",
	.pme_code = 0x000004D010,
	.pme_short_desc = "PMC1 Rewind Value saved",
	.pme_long_desc = "PMC1 Rewind Value saved",
},
[ POWER9_PME_PM_PMC2_OVERFLOW ] = {
	.pme_name = "PM_PMC2_OVERFLOW",
	.pme_code = 0x0000030010,
	.pme_short_desc = "Overflow from counter 2",
	.pme_long_desc = "Overflow from counter 2",
},
[ POWER9_PME_PM_PMC2_REWIND ] = {
	.pme_name = "PM_PMC2_REWIND",
	.pme_code = 0x0000030020,
	.pme_short_desc = "PMC2 Rewind Event (did not match condition)",
	.pme_long_desc = "PMC2 Rewind Event (did not match condition)",
},
[ POWER9_PME_PM_PMC2_SAVED ] = {
	.pme_name = "PM_PMC2_SAVED",
	.pme_code = 0x0000010022,
	.pme_short_desc = "PMC2 Rewind Value saved",
	.pme_long_desc = "PMC2 Rewind Value saved",
},
[ POWER9_PME_PM_PMC3_OVERFLOW ] = {
	.pme_name = "PM_PMC3_OVERFLOW",
	.pme_code = 0x0000040010,
	.pme_short_desc = "Overflow from counter 3",
	.pme_long_desc = "Overflow from counter 3",
},
[ POWER9_PME_PM_PMC3_REWIND ] = {
	.pme_name = "PM_PMC3_REWIND",
	.pme_code = 0x000001000A,
	.pme_short_desc = "PMC3 rewind event.",
	.pme_long_desc = "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change.",
},
[ POWER9_PME_PM_PMC3_SAVED ] = {
	.pme_name = "PM_PMC3_SAVED",
	.pme_code = 0x000004D012,
	.pme_short_desc = "PMC3 Rewind Value saved",
	.pme_long_desc = "PMC3 Rewind Value saved",
},
[ POWER9_PME_PM_PMC4_OVERFLOW ] = {
	.pme_name = "PM_PMC4_OVERFLOW",
	.pme_code = 0x0000010010,
	.pme_short_desc = "Overflow from counter 4",
	.pme_long_desc = "Overflow from counter 4",
},
[ POWER9_PME_PM_PMC4_REWIND ] = {
	.pme_name = "PM_PMC4_REWIND",
	.pme_code = 0x0000010020,
	.pme_short_desc = "PMC4 Rewind Event",
	.pme_long_desc = "PMC4 Rewind Event",
},
[ POWER9_PME_PM_PMC4_SAVED ] = {
	.pme_name = "PM_PMC4_SAVED",
	.pme_code = 0x0000030022,
	.pme_short_desc = "PMC4 Rewind Value saved (matched condition)",
	.pme_long_desc = "PMC4 Rewind Value saved (matched condition)",
},
[ POWER9_PME_PM_PMC5_OVERFLOW ] = {
	.pme_name = "PM_PMC5_OVERFLOW",
	.pme_code = 0x0000010024,
	.pme_short_desc = "Overflow from counter 5",
	.pme_long_desc = "Overflow from counter 5",
},
[ POWER9_PME_PM_PMC6_OVERFLOW ] = {
	.pme_name = "PM_PMC6_OVERFLOW",
	.pme_code = 0x0000030024,
	.pme_short_desc = "Overflow from counter 6",
	.pme_long_desc = "Overflow from counter 6",
},
[ POWER9_PME_PM_PROBE_NOP_DISP ] = {
	.pme_name = "PM_PROBE_NOP_DISP",
	.pme_code = 0x0000040014,
	.pme_short_desc = "ProbeNops dispatched",
	.pme_long_desc = "ProbeNops dispatched",
},
[ POWER9_PME_PM_PTE_PREFETCH ] = {
	.pme_name = "PM_PTE_PREFETCH",
	.pme_code = 0x000000F084,
	.pme_short_desc = "PTE prefetches",
	.pme_long_desc = "PTE prefetches",
},
[ POWER9_PME_PM_PTESYNC ] = {
	.pme_name = "PM_PTESYNC",
	.pme_code = 0x000000589C,
	.pme_short_desc = "ptesync instruction counted when the instruction is decoded and transmitted",
	.pme_long_desc = "ptesync instruction counted when the instruction is decoded and transmitted",
},
[ POWER9_PME_PM_PUMP_CPRED ] = {
	.pme_name = "PM_PUMP_CPRED",
	.pme_code = 0x0000010054,
	.pme_short_desc = "Pump prediction correct.",
	.pme_long_desc = "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER9_PME_PM_PUMP_MPRED ] = {
	.pme_name = "PM_PUMP_MPRED",
	.pme_code = 0x0000040052,
	.pme_short_desc = "Pump misprediction.",
	.pme_long_desc = "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER9_PME_PM_RADIX_PWC_L1_HIT ] = {
	.pme_name = "PM_RADIX_PWC_L1_HIT",
	.pme_code = 0x000001F056,
	.pme_short_desc = "A radix translation attempt missed in the TLB and only the first level page walk cache was a hit.",
	.pme_long_desc = "A radix translation attempt missed in the TLB and only the first level page walk cache was a hit.",
},
[ POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L2 ] = {
	.pme_name = "PM_RADIX_PWC_L1_PDE_FROM_L2",
	.pme_code = 0x000002D026,
	.pme_short_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache",
	.pme_long_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L2 data cache",
},
[ POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3MISS ] = {
	.pme_name = "PM_RADIX_PWC_L1_PDE_FROM_L3MISS",
	.pme_code = 0x000004F056,
	.pme_short_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache.",
	.pme_long_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant memory or another core's cache",
},
[ POWER9_PME_PM_RADIX_PWC_L1_PDE_FROM_L3 ] = {
	.pme_name = "PM_RADIX_PWC_L1_PDE_FROM_L3",
	.pme_code = 0x000003F058,
	.pme_short_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache",
	.pme_long_desc = "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache",
},
[ POWER9_PME_PM_RADIX_PWC_L2_HIT ] = {
	.pme_name = "PM_RADIX_PWC_L2_HIT",
	.pme_code = 0x000002D024,
	.pme_short_desc = "A radix translation attempt missed in the TLB but hit on both the first and second levels of page walk cache.",
	.pme_long_desc = "A radix translation attempt missed in the TLB but hit on both the first and second levels of page walk cache.",
},
[ POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L2 ] = {
	.pme_name = "PM_RADIX_PWC_L2_PDE_FROM_L2",
	.pme_code = 0x000002D028,
	.pme_short_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache",
	.pme_long_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache",
},
[ POWER9_PME_PM_RADIX_PWC_L2_PDE_FROM_L3 ] = {
	.pme_name = "PM_RADIX_PWC_L2_PDE_FROM_L3",
	.pme_code = 0x000003F05A,
	.pme_short_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache",
	.pme_long_desc = "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache",
},
[ POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L2 ] = {
	.pme_name = "PM_RADIX_PWC_L2_PTE_FROM_L2",
	.pme_code = 0x000001F058,
	.pme_short_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache.",
	.pme_long_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation",
},
[ POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3MISS ] = {
	.pme_name = "PM_RADIX_PWC_L2_PTE_FROM_L3MISS",
	.pme_code = 0x000004F05C,
	.pme_short_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache.",
	.pme_long_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from beyond the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation. The source could be local/remote/distant memory or another core's cache",
},
[ POWER9_PME_PM_RADIX_PWC_L2_PTE_FROM_L3 ] = {
	.pme_name = "PM_RADIX_PWC_L2_PTE_FROM_L3",
	.pme_code = 0x000004F058,
	.pme_short_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache.",
	.pme_long_desc = "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation",
},
[ POWER9_PME_PM_RADIX_PWC_L3_HIT ] = {
	.pme_name = "PM_RADIX_PWC_L3_HIT",
	.pme_code = 0x000003F056,
	.pme_short_desc = "A radix translation attempt missed in the TLB but hit on the first, second, and third levels of page walk cache.",
	.pme_long_desc = "A radix translation attempt missed in the TLB but hit on the first, second, and third levels of page walk cache.",
},
[ POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L2 ] = {
	.pme_name = "PM_RADIX_PWC_L3_PDE_FROM_L2",
	.pme_code = 0x000002D02A,
	.pme_short_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache",
	.pme_long_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache",
},
[ POWER9_PME_PM_RADIX_PWC_L3_PDE_FROM_L3 ] = {
	.pme_name = "PM_RADIX_PWC_L3_PDE_FROM_L3",
	.pme_code = 0x000001F15C,
	.pme_short_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache",
	.pme_long_desc = "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache",
},
[ POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L2 ] = {
	.pme_name = "PM_RADIX_PWC_L3_PTE_FROM_L2",
	.pme_code = 0x000002D02E,
	.pme_short_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache.",
	.pme_long_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation",
},
[ POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3MISS ] = {
	.pme_name = "PM_RADIX_PWC_L3_PTE_FROM_L3MISS",
	.pme_code = 0x000004F05E,
	.pme_short_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache.",
	.pme_long_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation. The source could be local/remote/distant memory or another core's cache",
},
[ POWER9_PME_PM_RADIX_PWC_L3_PTE_FROM_L3 ] = {
	.pme_name = "PM_RADIX_PWC_L3_PTE_FROM_L3",
	.pme_code = 0x000003F05E,
	.pme_short_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache.",
	.pme_long_desc = "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation",
},
[ POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L2 ] = {
	.pme_name = "PM_RADIX_PWC_L4_PTE_FROM_L2",
	.pme_code = 0x000001F05A,
	.pme_short_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache.",
	.pme_long_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache. This is the deepest level of PWC possible for a translation",
},
[ POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3MISS ] = {
	.pme_name = "PM_RADIX_PWC_L4_PTE_FROM_L3MISS",
	.pme_code = 0x000003F054,
	.pme_short_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache.",
	.pme_long_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from beyond the core's L3 data cache. This is the deepest level of PWC possible for a translation. The source could be local/remote/distant memory or another core's cache",
},
[ POWER9_PME_PM_RADIX_PWC_L4_PTE_FROM_L3 ] = {
	.pme_name = "PM_RADIX_PWC_L4_PTE_FROM_L3",
	.pme_code = 0x000004F05A,
	.pme_short_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache.",
	.pme_long_desc = "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache. This is the deepest level of PWC possible for a translation",
},
[ POWER9_PME_PM_RADIX_PWC_MISS ] = {
	.pme_name = "PM_RADIX_PWC_MISS",
	.pme_code = 0x000004F054,
	.pme_short_desc = "A radix translation attempt missed in the TLB and all levels of page walk cache.",
	.pme_long_desc = "A radix translation attempt missed in the TLB and all levels of page walk cache.",
},
[ POWER9_PME_PM_RC0_BUSY ] = {
	.pme_name = "PM_RC0_BUSY",
	.pme_code = 0x000001608C,
	.pme_short_desc = "RC mach 0 Busy.",
	.pme_long_desc = "RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point)",
},
[ POWER9_PME_PM_RC0_BUSY_ALT ] = {
	.pme_name = "PM_RC0_BUSY_ALT",
	.pme_code = 0x000002608C,
	.pme_short_desc = "RC mach 0 Busy.",
	.pme_long_desc = "RC mach 0 Busy. Used by PMU to sample ave RC lifetime (mach0 used as sample point)",
},
[ POWER9_PME_PM_RC_USAGE ] = {
	.pme_name = "PM_RC_USAGE",
	.pme_code = 0x000001688C,
	.pme_short_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each RC machine busy.",
	.pme_long_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running",
},
[ POWER9_PME_PM_RD_CLEARING_SC ] = {
	.pme_name = "PM_RD_CLEARING_SC",
	.pme_code = 0x00000468A6,
	.pme_short_desc = "Read clearing SC",
	.pme_long_desc = "Read clearing SC",
},
[ POWER9_PME_PM_RD_FORMING_SC ] = {
	.pme_name = "PM_RD_FORMING_SC",
	.pme_code = 0x00000460A6,
	.pme_short_desc = "Read forming SC",
	.pme_long_desc = "Read forming SC",
},
[ POWER9_PME_PM_RD_HIT_PF ] = {
	.pme_name = "PM_RD_HIT_PF",
	.pme_code = 0x00000268A8,
	.pme_short_desc = "RD machine hit L3 PF machine",
	.pme_long_desc = "RD machine hit L3 PF machine",
},
[ POWER9_PME_PM_RUN_CYC_SMT2_MODE ] = {
	.pme_name = "PM_RUN_CYC_SMT2_MODE",
	.pme_code = 0x000003006C,
	.pme_short_desc = "Cycles in which this thread's run latch is set and the core is in SMT2 mode",
	.pme_long_desc = "Cycles in which this thread's run latch is set and the core is in SMT2 mode",
},
[ POWER9_PME_PM_RUN_CYC_SMT4_MODE ] = {
	.pme_name = "PM_RUN_CYC_SMT4_MODE",
	.pme_code = 0x000002006C,
	.pme_short_desc = "Cycles in which this thread's run latch is set and the core is in SMT4 mode",
	.pme_long_desc = "Cycles in which this thread's run latch is set and the core is in SMT4 mode",
},
[ POWER9_PME_PM_RUN_CYC_ST_MODE ] = {
	.pme_name = "PM_RUN_CYC_ST_MODE",
	.pme_code = 0x000001006C,
	.pme_short_desc = "Cycles run latch is set and core is in ST mode",
	.pme_long_desc = "Cycles run latch is set and core is in ST mode",
},
[ POWER9_PME_PM_RUN_CYC ] = {
	.pme_name = "PM_RUN_CYC",
	.pme_code = 0x00000200F4,
	.pme_short_desc = "Run_cycles",
	.pme_long_desc = "Run_cycles",
},
[ POWER9_PME_PM_RUN_INST_CMPL ] = {
	.pme_name = "PM_RUN_INST_CMPL",
	.pme_code = 0x00000400FA,
	.pme_short_desc = "Run_Instructions",
	.pme_long_desc = "Run_Instructions",
},
[ POWER9_PME_PM_RUN_PURR ] = {
	.pme_name = "PM_RUN_PURR",
	.pme_code = 0x00000400F4,
	.pme_short_desc = "Run_PURR",
	.pme_long_desc = "Run_PURR",
},
[ POWER9_PME_PM_RUN_SPURR ] = {
	.pme_name = "PM_RUN_SPURR",
	.pme_code = 0x0000010008,
	.pme_short_desc = "Run SPURR",
	.pme_long_desc = "Run SPURR",
},
[ POWER9_PME_PM_S2Q_FULL ] = {
	.pme_name = "PM_S2Q_FULL",
	.pme_code = 0x000000E080,
	.pme_short_desc = "Cycles during which the S2Q is full",
	.pme_long_desc = "Cycles during which the S2Q is full",
},
[ POWER9_PME_PM_SCALAR_FLOP_CMPL ] = {
	.pme_name = "PM_SCALAR_FLOP_CMPL",
	.pme_code = 0x0000045056,
	.pme_short_desc = "Scalar flop operation completed",
	.pme_long_desc = "Scalar flop operation completed",
},
[ POWER9_PME_PM_SHL_CREATED ] = {
	.pme_name = "PM_SHL_CREATED",
	.pme_code = 0x000000508C,
	.pme_short_desc = "Store-Hit-Load Table Entry Created",
	.pme_long_desc = "Store-Hit-Load Table Entry Created",
},
[ POWER9_PME_PM_SHL_ST_DEP_CREATED ] = {
	.pme_name = "PM_SHL_ST_DEP_CREATED",
	.pme_code = 0x000000588C,
	.pme_short_desc = "Store-Hit-Load Table Read Hit with entry Enabled",
	.pme_long_desc = "Store-Hit-Load Table Read Hit with entry Enabled",
},
[ POWER9_PME_PM_SHL_ST_DISABLE ] = {
	.pme_name = "PM_SHL_ST_DISABLE",
	.pme_code = 0x0000005090,
	.pme_short_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)",
	.pme_long_desc = "Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush)",
},
[ POWER9_PME_PM_SLB_TABLEWALK_CYC ] = {
	.pme_name = "PM_SLB_TABLEWALK_CYC",
	.pme_code = 0x000000F09C,
	.pme_short_desc = "Cycles when a tablewalk is pending on this thread on the SLB table",
	.pme_long_desc = "Cycles when a tablewalk is pending on this thread on the SLB table",
},
[ POWER9_PME_PM_SN0_BUSY ] = {
	.pme_name = "PM_SN0_BUSY",
	.pme_code = 0x0000016090,
	.pme_short_desc = "SN mach 0 Busy.",
	.pme_long_desc = "SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point)",
},
[ POWER9_PME_PM_SN0_BUSY_ALT ] = {
	.pme_name = "PM_SN0_BUSY_ALT",
	.pme_code = 0x0000026090,
	.pme_short_desc = "SN mach 0 Busy.",
	.pme_long_desc = "SN mach 0 Busy. Used by PMU to sample ave SN lifetime (mach0 used as sample point)",
},
[ POWER9_PME_PM_SN_HIT ] = {
	.pme_name = "PM_SN_HIT",
	.pme_code = 0x00000460A8,
	.pme_short_desc = "Any port snooper hit L3.",
	.pme_long_desc = "Any port snooper hit L3. Up to 4 can happen in a cycle but we only count 1",
},
[ POWER9_PME_PM_SN_INVL ] = {
	.pme_name = "PM_SN_INVL",
	.pme_code = 0x00000368A8,
	.pme_short_desc = "Any port snooper detects a store to a line in the Sx state and invalidates the line.",
	.pme_long_desc = "Any port snooper detects a store to a line in the Sx state and invalidates the line. Up to 4 can happen in a cycle but we only count 1",
},
[ POWER9_PME_PM_SN_MISS ] = {
	.pme_name = "PM_SN_MISS",
	.pme_code = 0x00000468A8,
	.pme_short_desc = "Any port snooper L3 miss or collision.",
	.pme_long_desc = "Any port snooper L3 miss or collision. Up to 4 can happen in a cycle but we only count 1",
},
[ POWER9_PME_PM_SNOOP_TLBIE ] = {
	.pme_name = "PM_SNOOP_TLBIE",
	.pme_code = 0x000000F880,
	.pme_short_desc = "TLBIE snoop",
	.pme_long_desc = "TLBIE snoop",
},
[ POWER9_PME_PM_SNP_TM_HIT_M ] = {
	.pme_name = "PM_SNP_TM_HIT_M",
	.pme_code = 0x00000360A6,
	.pme_short_desc = "Snp TM st hit M/Mu",
	.pme_long_desc = "Snp TM st hit M/Mu",
},
[ POWER9_PME_PM_SNP_TM_HIT_T ] = {
	.pme_name = "PM_SNP_TM_HIT_T",
	.pme_code = 0x00000368A6,
	.pme_short_desc = "Snp TM sthit T/Tn/Te",
	.pme_long_desc = "Snp TM sthit T/Tn/Te",
},
[ POWER9_PME_PM_SN_USAGE ] = {
	.pme_name = "PM_SN_USAGE",
	.pme_code = 0x000003688C,
	.pme_short_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy.",
	.pme_long_desc = "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running",
},
[ POWER9_PME_PM_SP_FLOP_CMPL ] = {
	.pme_name = "PM_SP_FLOP_CMPL",
	.pme_code = 0x000004505A,
	.pme_short_desc = "SP instruction completed",
	.pme_long_desc = "SP instruction completed",
},
[ POWER9_PME_PM_SRQ_EMPTY_CYC ] = {
	.pme_name = "PM_SRQ_EMPTY_CYC",
	.pme_code = 0x0000040008,
	.pme_short_desc = "Cycles in which the SRQ has at least one (out of four) empty slice",
	.pme_long_desc = "Cycles in which the SRQ has at least one (out of four) empty slice",
},
[ POWER9_PME_PM_SRQ_SYNC_CYC ] = {
	.pme_name = "PM_SRQ_SYNC_CYC",
	.pme_code = 0x000000D0AC,
	.pme_short_desc = "A sync is in the S2Q (edge detect to count)",
	.pme_long_desc = "A sync is in the S2Q (edge detect to count)",
},
[ POWER9_PME_PM_STALL_END_ICT_EMPTY ] = {
	.pme_name = "PM_STALL_END_ICT_EMPTY",
	.pme_code = 0x0000010028,
	.pme_short_desc = "The number a times the core transitioned from a stall to ICT-empty for this thread",
	.pme_long_desc = "The number a times the core transitioned from a stall to ICT-empty for this thread",
},
[ POWER9_PME_PM_ST_CAUSED_FAIL ] = {
	.pme_name = "PM_ST_CAUSED_FAIL",
	.pme_code = 0x000001608E,
	.pme_short_desc = "Non-TM Store caused any thread to fail",
	.pme_long_desc = "Non-TM Store caused any thread to fail",
},
[ POWER9_PME_PM_ST_CMPL ] = {
	.pme_name = "PM_ST_CMPL",
	.pme_code = 0x00000200F0,
	.pme_short_desc = "Stores completed from S2Q (2nd-level store queue).",
	.pme_long_desc = "Stores completed from S2Q (2nd-level store queue).",
},
[ POWER9_PME_PM_STCX_FAIL ] = {
	.pme_name = "PM_STCX_FAIL",
	.pme_code = 0x000001E058,
	.pme_short_desc = "stcx failed",
	.pme_long_desc = "stcx failed",
},
[ POWER9_PME_PM_STCX_FIN ] = {
	.pme_name = "PM_STCX_FIN",
	.pme_code = 0x000002E014,
	.pme_short_desc = "Number of stcx instructions finished.",
	.pme_long_desc = "Number of stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed",
},
[ POWER9_PME_PM_STCX_SUCCESS_CMPL ] = {
	.pme_name = "PM_STCX_SUCCESS_CMPL",
	.pme_code = 0x000000C8BC,
	.pme_short_desc = "Number of stcx instructions that completed successfully",
	.pme_long_desc = "Number of stcx instructions that completed successfully",
},
[ POWER9_PME_PM_ST_FIN ] = {
	.pme_name = "PM_ST_FIN",
	.pme_code = 0x0000020016,
	.pme_short_desc = "Store finish count.",
	.pme_long_desc = "Store finish count. Includes speculative activity",
},
[ POWER9_PME_PM_ST_FWD ] = {
	.pme_name = "PM_ST_FWD",
	.pme_code = 0x0000020018,
	.pme_short_desc = "Store forwards that finished",
	.pme_long_desc = "Store forwards that finished",
},
[ POWER9_PME_PM_ST_MISS_L1 ] = {
	.pme_name = "PM_ST_MISS_L1",
	.pme_code = 0x00000300F0,
	.pme_short_desc = "Store Missed L1",
	.pme_long_desc = "Store Missed L1",
},
[ POWER9_PME_PM_STOP_FETCH_PENDING_CYC ] = {
	.pme_name = "PM_STOP_FETCH_PENDING_CYC",
	.pme_code = 0x00000048A4,
	.pme_short_desc = "Fetching is stopped due to an incoming instruction that will result in a flush",
	.pme_long_desc = "Fetching is stopped due to an incoming instruction that will result in a flush",
},
/* See also alternate entries for 0000010000 / POWER9_PME_PM_SUSPENDED with code(s) 0000020000 0000030000 0000040000 at the bottom of this table. \n */
[ POWER9_PME_PM_SUSPENDED ] = {
	.pme_name = "PM_SUSPENDED",
	.pme_code = 0x0000010000,
	.pme_short_desc = "Counter OFF",
	.pme_long_desc = "Counter OFF",
},
[ POWER9_PME_PM_SYNC_MRK_BR_LINK ] = {
	.pme_name = "PM_SYNC_MRK_BR_LINK",
	.pme_code = 0x0000015152,
	.pme_short_desc = "Marked Branch and link branch that can cause a synchronous interrupt",
	.pme_long_desc = "Marked Branch and link branch that can cause a synchronous interrupt",
},
[ POWER9_PME_PM_SYNC_MRK_BR_MPRED ] = {
	.pme_name = "PM_SYNC_MRK_BR_MPRED",
	.pme_code = 0x000001515C,
	.pme_short_desc = "Marked Branch mispredict that can cause a synchronous interrupt",
	.pme_long_desc = "Marked Branch mispredict that can cause a synchronous interrupt",
},
[ POWER9_PME_PM_SYNC_MRK_FX_DIVIDE ] = {
	.pme_name = "PM_SYNC_MRK_FX_DIVIDE",
	.pme_code = 0x0000015156,
	.pme_short_desc = "Marked fixed point divide that can cause a synchronous interrupt",
	.pme_long_desc = "Marked fixed point divide that can cause a synchronous interrupt",
},
[ POWER9_PME_PM_SYNC_MRK_L2HIT ] = {
	.pme_name = "PM_SYNC_MRK_L2HIT",
	.pme_code = 0x0000015158,
	.pme_short_desc = "Marked L2 Hits that can throw a synchronous interrupt",
	.pme_long_desc = "Marked L2 Hits that can throw a synchronous interrupt",
},
[ POWER9_PME_PM_SYNC_MRK_L2MISS ] = {
	.pme_name = "PM_SYNC_MRK_L2MISS",
	.pme_code = 0x000001515A,
	.pme_short_desc = "Marked L2 Miss that can throw a synchronous interrupt",
	.pme_long_desc = "Marked L2 Miss that can throw a synchronous interrupt",
},
[ POWER9_PME_PM_SYNC_MRK_L3MISS ] = {
	.pme_name = "PM_SYNC_MRK_L3MISS",
	.pme_code = 0x0000015154,
	.pme_short_desc = "Marked L3 misses that can throw a synchronous interrupt",
	.pme_long_desc = "Marked L3 misses that can throw a synchronous interrupt",
},
[ POWER9_PME_PM_SYNC_MRK_PROBE_NOP ] = {
	.pme_name = "PM_SYNC_MRK_PROBE_NOP",
	.pme_code = 0x0000015150,
	.pme_short_desc = "Marked probeNops which can cause synchronous interrupts",
	.pme_long_desc = "Marked probeNops which can cause synchronous interrupts",
},
[ POWER9_PME_PM_SYS_PUMP_CPRED ] = {
	.pme_name = "PM_SYS_PUMP_CPRED",
	.pme_code = 0x0000030050,
	.pme_short_desc = "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER9_PME_PM_SYS_PUMP_MPRED_RTY ] = {
	.pme_name = "PM_SYS_PUMP_MPRED_RTY",
	.pme_code = 0x0000040050,
	.pme_short_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
	.pme_long_desc = "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER9_PME_PM_SYS_PUMP_MPRED ] = {
	.pme_name = "PM_SYS_PUMP_MPRED",
	.pme_code = 0x0000030052,
	.pme_short_desc = "Final Pump Scope (system) mispredicted.",
	.pme_long_desc = "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
},
[ POWER9_PME_PM_TABLEWALK_CYC_PREF ] = {
	.pme_name = "PM_TABLEWALK_CYC_PREF",
	.pme_code = 0x000000F884,
	.pme_short_desc = "tablewalk qualified for pte prefetches",
	.pme_long_desc = "tablewalk qualified for pte prefetches",
},
[ POWER9_PME_PM_TABLEWALK_CYC ] = {
	.pme_name = "PM_TABLEWALK_CYC",
	.pme_code = 0x0000010026,
	.pme_short_desc = "Cycles when an instruction tablewalk is active",
	.pme_long_desc = "Cycles when an instruction tablewalk is active",
},
[ POWER9_PME_PM_TAGE_CORRECT_TAKEN_CMPL ] = {
	.pme_name = "PM_TAGE_CORRECT_TAKEN_CMPL",
	.pme_code = 0x00000050B4,
	.pme_short_desc = "The TAGE overrode BHT direction prediction and it was correct.",
	.pme_long_desc = "The TAGE overrode BHT direction prediction and it was correct. Counted at completion for taken branches only",
},
[ POWER9_PME_PM_TAGE_CORRECT ] = {
	.pme_name = "PM_TAGE_CORRECT",
	.pme_code = 0x00000058B4,
	.pme_short_desc = "The TAGE overrode BHT direction prediction and it was correct.",
	.pme_long_desc = "The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time",
},
[ POWER9_PME_PM_TAGE_OVERRIDE_WRONG_SPEC ] = {
	.pme_name = "PM_TAGE_OVERRIDE_WRONG_SPEC",
	.pme_code = 0x00000058B8,
	.pme_short_desc = "The TAGE overrode BHT direction prediction and it was correct.",
	.pme_long_desc = "The TAGE overrode BHT direction prediction and it was correct. Includes taken and not taken and is counted at execution time",
},
[ POWER9_PME_PM_TAGE_OVERRIDE_WRONG ] = {
	.pme_name = "PM_TAGE_OVERRIDE_WRONG",
	.pme_code = 0x00000050B8,
	.pme_short_desc = "The TAGE overrode BHT direction prediction but it was incorrect.",
	.pme_long_desc = "The TAGE overrode BHT direction prediction but it was incorrect. Counted at completion for taken branches only",
},
[ POWER9_PME_PM_TAKEN_BR_MPRED_CMPL ] = {
	.pme_name = "PM_TAKEN_BR_MPRED_CMPL",
	.pme_code = 0x0000020056,
	.pme_short_desc = "Total number of taken branches that were incorrectly predicted as not-taken.",
	.pme_long_desc = "Total number of taken branches that were incorrectly predicted as not-taken. This event counts branches completed and does not include speculative instructions",
},
[ POWER9_PME_PM_TB_BIT_TRANS ] = {
	.pme_name = "PM_TB_BIT_TRANS",
	.pme_code = 0x00000300F8,
	.pme_short_desc = "timebase event",
	.pme_long_desc = "timebase event",
},
[ POWER9_PME_PM_TEND_PEND_CYC ] = {
	.pme_name = "PM_TEND_PEND_CYC",
	.pme_code = 0x000000E8B0,
	.pme_short_desc = "TEND latency per thread",
	.pme_long_desc = "TEND latency per thread",
},
[ POWER9_PME_PM_THRD_ALL_RUN_CYC ] = {
	.pme_name = "PM_THRD_ALL_RUN_CYC",
	.pme_code = 0x000002000C,
	.pme_short_desc = "Cycles in which all the threads have the run latch set",
	.pme_long_desc = "Cycles in which all the threads have the run latch set",
},
[ POWER9_PME_PM_THRD_CONC_RUN_INST ] = {
	.pme_name = "PM_THRD_CONC_RUN_INST",
	.pme_code = 0x00000300F4,
	.pme_short_desc = "PPC Instructions Finished by this thread when all threads in the core had the run-latch set",
	.pme_long_desc = "PPC Instructions Finished by this thread when all threads in the core had the run-latch set",
},
[ POWER9_PME_PM_THRD_PRIO_0_1_CYC ] = {
	.pme_name = "PM_THRD_PRIO_0_1_CYC",
	.pme_code = 0x00000040BC,
	.pme_short_desc = "Cycles thread running at priority level 0 or 1",
	.pme_long_desc = "Cycles thread running at priority level 0 or 1",
},
[ POWER9_PME_PM_THRD_PRIO_2_3_CYC ] = {
	.pme_name = "PM_THRD_PRIO_2_3_CYC",
	.pme_code = 0x00000048BC,
	.pme_short_desc = "Cycles thread running at priority level 2 or 3",
	.pme_long_desc = "Cycles thread running at priority level 2 or 3",
},
[ POWER9_PME_PM_THRD_PRIO_4_5_CYC ] = {
	.pme_name = "PM_THRD_PRIO_4_5_CYC",
	.pme_code = 0x0000005080,
	.pme_short_desc = "Cycles thread running at priority level 4 or 5",
	.pme_long_desc = "Cycles thread running at priority level 4 or 5",
},
[ POWER9_PME_PM_THRD_PRIO_6_7_CYC ] = {
	.pme_name = "PM_THRD_PRIO_6_7_CYC",
	.pme_code = 0x0000005880,
	.pme_short_desc = "Cycles thread running at priority level 6 or 7",
	.pme_long_desc = "Cycles thread running at priority level 6 or 7",
},
[ POWER9_PME_PM_THRESH_ACC ] = {
	.pme_name = "PM_THRESH_ACC",
	.pme_code = 0x0000024154,
	.pme_short_desc = "This event increments every time the threshold event counter ticks.",
	.pme_long_desc = "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs.",
},
[ POWER9_PME_PM_THRESH_EXC_1024 ] = {
	.pme_name = "PM_THRESH_EXC_1024",
	.pme_code = 0x00000301EA,
	.pme_short_desc = "Threshold counter exceeded a value of 1024",
	.pme_long_desc = "Threshold counter exceeded a value of 1024",
},
[ POWER9_PME_PM_THRESH_EXC_128 ] = {
	.pme_name = "PM_THRESH_EXC_128",
	.pme_code = 0x00000401EA,
	.pme_short_desc = "Threshold counter exceeded a value of 128",
	.pme_long_desc = "Threshold counter exceeded a value of 128",
},
[ POWER9_PME_PM_THRESH_EXC_2048 ] = {
	.pme_name = "PM_THRESH_EXC_2048",
	.pme_code = 0x00000401EC,
	.pme_short_desc = "Threshold counter exceeded a value of 2048",
	.pme_long_desc = "Threshold counter exceeded a value of 2048",
},
[ POWER9_PME_PM_THRESH_EXC_256 ] = {
	.pme_name = "PM_THRESH_EXC_256",
	.pme_code = 0x00000101E8,
	.pme_short_desc = "Threshold counter exceed a count of 256",
	.pme_long_desc = "Threshold counter exceed a count of 256",
},
[ POWER9_PME_PM_THRESH_EXC_32 ] = {
	.pme_name = "PM_THRESH_EXC_32",
	.pme_code = 0x00000201E6,
	.pme_short_desc = "Threshold counter exceeded a value of 32",
	.pme_long_desc = "Threshold counter exceeded a value of 32",
},
[ POWER9_PME_PM_THRESH_EXC_4096 ] = {
	.pme_name = "PM_THRESH_EXC_4096",
	.pme_code = 0x00000101E6,
	.pme_short_desc = "Threshold counter exceed a count of 4096",
	.pme_long_desc = "Threshold counter exceed a count of 4096",
},
[ POWER9_PME_PM_THRESH_EXC_512 ] = {
	.pme_name = "PM_THRESH_EXC_512",
	.pme_code = 0x00000201E8,
	.pme_short_desc = "Threshold counter exceeded a value of 512",
	.pme_long_desc = "Threshold counter exceeded a value of 512",
},
[ POWER9_PME_PM_THRESH_EXC_64 ] = {
	.pme_name = "PM_THRESH_EXC_64",
	.pme_code = 0x00000301E8,
	.pme_short_desc = "Threshold counter exceeded a value of 64",
	.pme_long_desc = "Threshold counter exceeded a value of 64",
},
[ POWER9_PME_PM_THRESH_MET ] = {
	.pme_name = "PM_THRESH_MET",
	.pme_code = 0x00000101EC,
	.pme_short_desc = "threshold exceeded",
	.pme_long_desc = "threshold exceeded",
},
[ POWER9_PME_PM_THRESH_NOT_MET ] = {
	.pme_name = "PM_THRESH_NOT_MET",
	.pme_code = 0x000004016E,
	.pme_short_desc = "Threshold counter did not meet threshold",
	.pme_long_desc = "Threshold counter did not meet threshold",
},
[ POWER9_PME_PM_TLB_HIT ] = {
	.pme_name = "PM_TLB_HIT",
	.pme_code = 0x000001F054,
	.pme_short_desc = "Number of times the TLB had the data required by the instruction.",
	.pme_long_desc = "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT",
},
[ POWER9_PME_PM_TLBIE_FIN ] = {
	.pme_name = "PM_TLBIE_FIN",
	.pme_code = 0x0000030058,
	.pme_short_desc = "tlbie finished",
	.pme_long_desc = "tlbie finished",
},
[ POWER9_PME_PM_TLB_MISS ] = {
	.pme_name = "PM_TLB_MISS",
	.pme_code = 0x0000020066,
	.pme_short_desc = "TLB Miss (I + D)",
	.pme_long_desc = "TLB Miss (I + D)",
},
[ POWER9_PME_PM_TM_ABORTS ] = {
	.pme_name = "PM_TM_ABORTS",
	.pme_code = 0x0000030056,
	.pme_short_desc = "Number of TM transactions aborted",
	.pme_long_desc = "Number of TM transactions aborted",
},
[ POWER9_PME_PM_TMA_REQ_L2 ] = {
	.pme_name = "PM_TMA_REQ_L2",
	.pme_code = 0x000000E0A4,
	.pme_short_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding",
	.pme_long_desc = "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding",
},
[ POWER9_PME_PM_TM_CAM_OVERFLOW ] = {
	.pme_name = "PM_TM_CAM_OVERFLOW",
	.pme_code = 0x00000168A6,
	.pme_short_desc = "L3 TM cam overflow during L2 co of SC",
	.pme_long_desc = "L3 TM cam overflow during L2 co of SC",
},
[ POWER9_PME_PM_TM_CAP_OVERFLOW ] = {
	.pme_name = "PM_TM_CAP_OVERFLOW",
	.pme_code = 0x000004608E,
	.pme_short_desc = "TM Footprint Capacity Overflow",
	.pme_long_desc = "TM Footprint Capacity Overflow",
},
[ POWER9_PME_PM_TM_FAIL_CONF_NON_TM ] = {
	.pme_name = "PM_TM_FAIL_CONF_NON_TM",
	.pme_code = 0x00000028A8,
	.pme_short_desc = "TM aborted because a conflict occurred with a non-transactional access by another processor",
	.pme_long_desc = "TM aborted because a conflict occurred with a non-transactional access by another processor",
},
[ POWER9_PME_PM_TM_FAIL_CONF_TM ] = {
	.pme_name = "PM_TM_FAIL_CONF_TM",
	.pme_code = 0x00000020AC,
	.pme_short_desc = "TM aborted because a conflict occurred with another transaction.",
	.pme_long_desc = "TM aborted because a conflict occurred with another transaction.",
},
[ POWER9_PME_PM_TM_FAIL_FOOTPRINT_OVERFLOW ] = {
	.pme_name = "PM_TM_FAIL_FOOTPRINT_OVERFLOW",
	.pme_code = 0x00000020A8,
	.pme_short_desc = "TM aborted because the tracking limit for transactional storage accesses was exceeded.",
	.pme_long_desc = "TM aborted because the tracking limit for transactional storage accesses was exceeded.. Asynchronous",
},
[ POWER9_PME_PM_TM_FAIL_NON_TX_CONFLICT ] = {
	.pme_name = "PM_TM_FAIL_NON_TX_CONFLICT",
	.pme_code = 0x000000E0B0,
	.pme_short_desc = "Non transactional conflict from LSU, gets reported to TEXASR",
	.pme_long_desc = "Non transactional conflict from LSU, gets reported to TEXASR",
},
[ POWER9_PME_PM_TM_FAIL_SELF ] = {
	.pme_name = "PM_TM_FAIL_SELF",
	.pme_code = 0x00000028AC,
	.pme_short_desc = "TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally; a dcbf, dcbi, or icbi specify- ing a block that was previously accessed transactionally; a dcbst specifying a block that was previously written transactionally; or a tlbie that specifies a translation that was pre- viously used transactionally",
	.pme_long_desc = "TM aborted because a self-induced conflict occurred in Suspended state, due to one of the following: a store to a storage location that was previously accessed transactionally; a dcbf, dcbi, or icbi specify- ing a block that was previously accessed transactionally; a dcbst specifying a block that was previously written transactionally; or a tlbie that specifies a translation that was pre- viously used transactionally",
},
[ POWER9_PME_PM_TM_FAIL_TLBIE ] = {
	.pme_name = "PM_TM_FAIL_TLBIE",
	.pme_code = 0x000000E0AC,
	.pme_short_desc = "Transaction failed because there was a TLBIE hit in the bloom filter",
	.pme_long_desc = "Transaction failed because there was a TLBIE hit in the bloom filter",
},
[ POWER9_PME_PM_TM_FAIL_TX_CONFLICT ] = {
	.pme_name = "PM_TM_FAIL_TX_CONFLICT",
	.pme_code = 0x000000E8AC,
	.pme_short_desc = "Transactional conflict from LSU, gets reported to TEXASR",
	.pme_long_desc = "Transactional conflict from LSU, gets reported to TEXASR",
},
[ POWER9_PME_PM_TM_FAV_CAUSED_FAIL ] = {
	.pme_name = "PM_TM_FAV_CAUSED_FAIL",
	.pme_code = 0x000002688E,
	.pme_short_desc = "TM Load (fav) caused another thread to fail",
	.pme_long_desc = "TM Load (fav) caused another thread to fail",
},
[ POWER9_PME_PM_TM_FAV_TBEGIN ] = {
	.pme_name = "PM_TM_FAV_TBEGIN",
	.pme_code = 0x000000209C,
	.pme_short_desc = "Dispatch time Favored tbegin",
	.pme_long_desc = "Dispatch time Favored tbegin",
},
[ POWER9_PME_PM_TM_LD_CAUSED_FAIL ] = {
	.pme_name = "PM_TM_LD_CAUSED_FAIL",
	.pme_code = 0x000001688E,
	.pme_short_desc = "Non-TM Load caused any thread to fail",
	.pme_long_desc = "Non-TM Load caused any thread to fail",
},
[ POWER9_PME_PM_TM_LD_CONF ] = {
	.pme_name = "PM_TM_LD_CONF",
	.pme_code = 0x000002608E,
	.pme_short_desc = "TM Load (fav or non-fav) ran into conflict (failed)",
	.pme_long_desc = "TM Load (fav or non-fav) ran into conflict (failed)",
},
[ POWER9_PME_PM_TM_NESTED_TBEGIN ] = {
	.pme_name = "PM_TM_NESTED_TBEGIN",
	.pme_code = 0x00000020A0,
	.pme_short_desc = "Completion Tm nested tbegin",
	.pme_long_desc = "Completion Tm nested tbegin",
},
[ POWER9_PME_PM_TM_NESTED_TEND ] = {
	.pme_name = "PM_TM_NESTED_TEND",
	.pme_code = 0x0000002098,
	.pme_short_desc = "Completion time nested tend",
	.pme_long_desc = "Completion time nested tend",
},
[ POWER9_PME_PM_TM_NON_FAV_TBEGIN ] = {
	.pme_name = "PM_TM_NON_FAV_TBEGIN",
	.pme_code = 0x000000289C,
	.pme_short_desc = "Dispatch time non favored tbegin",
	.pme_long_desc = "Dispatch time non favored tbegin",
},
[ POWER9_PME_PM_TM_OUTER_TBEGIN_DISP ] = {
	.pme_name = "PM_TM_OUTER_TBEGIN_DISP",
	.pme_code = 0x000004E05E,
	.pme_short_desc = "Number of outer tbegin instructions dispatched.",
	.pme_long_desc = "Number of outer tbegin instructions dispatched. The dispatch unit determines whether the tbegin instruction is outer or nested. This is a speculative count, which includes flushed instructions",
},
[ POWER9_PME_PM_TM_OUTER_TBEGIN ] = {
	.pme_name = "PM_TM_OUTER_TBEGIN",
	.pme_code = 0x0000002094,
	.pme_short_desc = "Completion time outer tbegin",
	.pme_long_desc = "Completion time outer tbegin",
},
[ POWER9_PME_PM_TM_OUTER_TEND ] = {
	.pme_name = "PM_TM_OUTER_TEND",
	.pme_code = 0x0000002894,
	.pme_short_desc = "Completion time outer tend",
	.pme_long_desc = "Completion time outer tend",
},
[ POWER9_PME_PM_TM_PASSED ] = {
	.pme_name = "PM_TM_PASSED",
	.pme_code = 0x000002E052,
	.pme_short_desc = "Number of TM transactions that passed",
	.pme_long_desc = "Number of TM transactions that passed",
},
[ POWER9_PME_PM_TM_RST_SC ] = {
	.pme_name = "PM_TM_RST_SC",
	.pme_code = 0x00000268A6,
	.pme_short_desc = "TM-snp rst RM SC",
	.pme_long_desc = "TM-snp rst RM SC",
},
[ POWER9_PME_PM_TM_SC_CO ] = {
	.pme_name = "PM_TM_SC_CO",
	.pme_code = 0x00000160A6,
	.pme_short_desc = "L3 castout TM SC line",
	.pme_long_desc = "L3 castout TM SC line",
},
[ POWER9_PME_PM_TM_ST_CAUSED_FAIL ] = {
	.pme_name = "PM_TM_ST_CAUSED_FAIL",
	.pme_code = 0x000003688E,
	.pme_short_desc = "TM Store (fav or non-fav) caused another thread to fail",
	.pme_long_desc = "TM Store (fav or non-fav) caused another thread to fail",
},
[ POWER9_PME_PM_TM_ST_CONF ] = {
	.pme_name = "PM_TM_ST_CONF",
	.pme_code = 0x000003608E,
	.pme_short_desc = "TM Store (fav or non-fav) ran into conflict (failed)",
	.pme_long_desc = "TM Store (fav or non-fav) ran into conflict (failed)",
},
[ POWER9_PME_PM_TM_TABORT_TRECLAIM ] = {
	.pme_name = "PM_TM_TABORT_TRECLAIM",
	.pme_code = 0x0000002898,
	.pme_short_desc = "Completion time tabortnoncd, tabortcd, treclaim",
	.pme_long_desc = "Completion time tabortnoncd, tabortcd, treclaim",
},
[ POWER9_PME_PM_TM_TRANS_RUN_CYC ] = {
	.pme_name = "PM_TM_TRANS_RUN_CYC",
	.pme_code = 0x0000010060,
	.pme_short_desc = "run cycles in transactional state",
	.pme_long_desc = "run cycles in transactional state",
},
[ POWER9_PME_PM_TM_TRANS_RUN_INST ] = {
	.pme_name = "PM_TM_TRANS_RUN_INST",
	.pme_code = 0x0000030060,
	.pme_short_desc = "Run instructions completed in transactional state (gated by the run latch)",
	.pme_long_desc = "Run instructions completed in transactional state (gated by the run latch)",
},
[ POWER9_PME_PM_TM_TRESUME ] = {
	.pme_name = "PM_TM_TRESUME",
	.pme_code = 0x00000020A4,
	.pme_short_desc = "TM resume instruction completed",
	.pme_long_desc = "TM resume instruction completed",
},
[ POWER9_PME_PM_TM_TSUSPEND ] = {
	.pme_name = "PM_TM_TSUSPEND",
	.pme_code = 0x00000028A0,
	.pme_short_desc = "TM suspend instruction completed",
	.pme_long_desc = "TM suspend instruction completed",
},
[ POWER9_PME_PM_TM_TX_PASS_RUN_CYC ] = {
	.pme_name = "PM_TM_TX_PASS_RUN_CYC",
	.pme_code = 0x000002E012,
	.pme_short_desc = "cycles spent in successful transactions",
	.pme_long_desc = "cycles spent in successful transactions",
},
[ POWER9_PME_PM_TM_TX_PASS_RUN_INST ] = {
	.pme_name = "PM_TM_TX_PASS_RUN_INST",
	.pme_code = 0x000004E014,
	.pme_short_desc = "Run instructions spent in successful transactions",
	.pme_long_desc = "Run instructions spent in successful transactions",
},
[ POWER9_PME_PM_VECTOR_FLOP_CMPL ] = {
	.pme_name = "PM_VECTOR_FLOP_CMPL",
	.pme_code = 0x000004D058,
	.pme_short_desc = "Vector FP instruction completed",
	.pme_long_desc = "Vector FP instruction completed",
},
[ POWER9_PME_PM_VECTOR_LD_CMPL ] = {
	.pme_name = "PM_VECTOR_LD_CMPL",
	.pme_code = 0x0000044054,
	.pme_short_desc = "Number of vector load instructions completed",
	.pme_long_desc = "Number of vector load instructions completed",
},
[ POWER9_PME_PM_VECTOR_ST_CMPL ] = {
	.pme_name = "PM_VECTOR_ST_CMPL",
	.pme_code = 0x0000044056,
	.pme_short_desc = "Number of vector store instructions completed",
	.pme_long_desc = "Number of vector store instructions completed",
},
[ POWER9_PME_PM_VSU_DP_FSQRT_FDIV ] = {
	.pme_name = "PM_VSU_DP_FSQRT_FDIV",
	.pme_code = 0x000003D058,
	.pme_short_desc = "vector versions of fdiv,fsqrt",
	.pme_long_desc = "vector versions of fdiv,fsqrt",
},
[ POWER9_PME_PM_VSU_FIN ] = {
	.pme_name = "PM_VSU_FIN",
	.pme_code = 0x000002505C,
	.pme_short_desc = "VSU instruction finished.",
	.pme_long_desc = "VSU instruction finished. Up to 4 per cycle",
},
[ POWER9_PME_PM_VSU_FSQRT_FDIV ] = {
	.pme_name = "PM_VSU_FSQRT_FDIV",
	.pme_code = 0x000004D04E,
	.pme_short_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only",
	.pme_long_desc = "four flops operation (fdiv,fsqrt) Scalar Instructions only",
},
[ POWER9_PME_PM_VSU_NON_FLOP_CMPL ] = {
	.pme_name = "PM_VSU_NON_FLOP_CMPL",
	.pme_code = 0x000004D050,
	.pme_short_desc = "Non FLOP operation completed",
	.pme_long_desc = "Non FLOP operation completed",
},
[ POWER9_PME_PM_XLATE_HPT_MODE ] = {
	.pme_name = "PM_XLATE_HPT_MODE",
	.pme_code = 0x000000F098,
	.pme_short_desc = "LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode)",
	.pme_long_desc = "LSU reports every cycle the thread is in HPT translation mode (as opposed to radix mode)",
},
[ POWER9_PME_PM_XLATE_MISS ] = {
	.pme_name = "PM_XLATE_MISS",
	.pme_code = 0x000000F89C,
	.pme_short_desc = "The LSU requested a line from L2 for translation.",
	.pme_long_desc = "The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions",
},
[ POWER9_PME_PM_XLATE_RADIX_MODE ] = {
	.pme_name = "PM_XLATE_RADIX_MODE",
	.pme_code = 0x000000F898,
	.pme_short_desc = "LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode)",
	.pme_long_desc = "LSU reports every cycle the thread is in radix translation mode (as opposed to HPT mode)",
},
[ POWER9_PME_PM_BR_2PATH_ALT ] = {
	.pme_name = "PM_BR_2PATH_ALT",
	.pme_code = 0x0000040036,
	.pme_short_desc = "Branches that are not strongly biased",
	.pme_long_desc = "Branches that are not strongly biased",
},
[ POWER9_PME_PM_CYC_ALT ] = {
	.pme_name = "PM_CYC_ALT",
	.pme_code = 0x000002001E,
	.pme_short_desc = "Processor cycles",
	.pme_long_desc = "Processor cycles",
},
[ POWER9_PME_PM_CYC_ALT2 ] = {
	.pme_name = "PM_CYC_ALT2",
	.pme_code = 0x000003001E,
	.pme_short_desc = "Processor cycles",
	.pme_long_desc = "Processor cycles",
},
[ POWER9_PME_PM_CYC_ALT3 ] = {
	.pme_name = "PM_CYC_ALT3",
	.pme_code = 0x000004001E,
	.pme_short_desc = "Processor cycles",
	.pme_long_desc = "Processor cycles",
},
[ POWER9_PME_PM_INST_CMPL_ALT ] = {
	.pme_name = "PM_INST_CMPL_ALT",
	.pme_code = 0x0000020002,
	.pme_short_desc = "Number of PowerPC Instructions that completed.",
	.pme_long_desc = "Number of PowerPC Instructions that completed.",
},
[ POWER9_PME_PM_INST_CMPL_ALT2 ] = {
	.pme_name = "PM_INST_CMPL_ALT2",
	.pme_code = 0x0000030002,
	.pme_short_desc = "Number of PowerPC Instructions that completed.",
	.pme_long_desc = "Number of PowerPC Instructions that completed.",
},
[ POWER9_PME_PM_INST_CMPL_ALT3 ] = {
	.pme_name = "PM_INST_CMPL_ALT3",
	.pme_code = 0x0000040002,
	.pme_short_desc = "Number of PowerPC Instructions that completed.",
	.pme_long_desc = "Number of PowerPC Instructions that completed.",
},
[ POWER9_PME_PM_INST_DISP_ALT ] = {
	.pme_name = "PM_INST_DISP_ALT",
	.pme_code = 0x00000300F2,
	.pme_short_desc = "# PPC Dispatched",
	.pme_long_desc = "# PPC Dispatched",
},
[ POWER9_PME_PM_LD_MISS_L1_ALT ] = {
	.pme_name = "PM_LD_MISS_L1_ALT",
	.pme_code = 0x00000400F0,
	.pme_short_desc = "Load Missed L1, counted at execution time (can be greater than loads finished).",
	.pme_long_desc = "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.",
},
[ POWER9_PME_PM_SUSPENDED_ALT ] = {
	.pme_name = "PM_SUSPENDED_ALT",
	.pme_code = 0x0000020000,
	.pme_short_desc = "Counter OFF",
	.pme_long_desc = "Counter OFF",
},
[ POWER9_PME_PM_SUSPENDED_ALT2 ] = {
	.pme_name = "PM_SUSPENDED_ALT2",
	.pme_code = 0x0000030000,
	.pme_short_desc = "Counter OFF",
	.pme_long_desc = "Counter OFF",
},
[ POWER9_PME_PM_SUSPENDED_ALT3 ] = {
	.pme_name = "PM_SUSPENDED_ALT3",
	.pme_code = 0x0000040000,
	.pme_short_desc = "Counter OFF",
	.pme_long_desc = "Counter OFF",
},
/* total 957 */
};
#endif
