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#
# Xilinx Core Generator version 14.7
# Date: Fri Dec 19 01:18:02 2014
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:cordic:5.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7k410t
SET devicefamily = kintex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg900
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT CORDIC xilinx.com:ip:cordic:5.0
# END Select
# BEGIN Parameters
CSET aclken=false
CSET architectural_configuration=Parallel
CSET aresetn=true
CSET cartesian_has_tlast=true
CSET cartesian_has_tuser=false
CSET cartesian_tuser_width=1
CSET coarse_rotation=true
CSET compensation_scaling=Embedded_Multiplier
CSET component_name=complex_to_magphase
CSET data_format=SignedFraction
CSET flow_control=Blocking
CSET functional_selection=Translate
CSET input_width=16
CSET iterations=0
CSET optimize_goal=Performance
CSET out_tlast_behv=Pass_Cartesian_TLAST
CSET out_tready=true
CSET output_width=16
CSET phase_format=Scaled_Radians
CSET phase_has_tlast=false
CSET phase_has_tuser=false
CSET phase_tuser_width=1
CSET pipelining_mode=Maximum
CSET precision=0
CSET round_mode=Round_Pos_Neg_Inf
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-07-22T10:47:11Z
# END Extra information
GENERATE
# CRC: dcc1ac4f
