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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
// "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____40.000______0.000______50.0______312.078____259.584
// CLK_OUT2___100.000______0.000______50.0______255.594____259.584
// CLK_OUT3___200.000______0.000______50.0______225.630____259.584
//
//----------------------------------------------------------------------------
// "Input Clock   Freq (MHz)    Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________40.000____________0.010

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

  b205_clk_gen instance_name
   (// Clock in ports
    .CLK_IN1_40(CLK_IN1_40),      // IN
    // Clock out ports
    .CLK_OUT1_40_int(CLK_OUT1_40_int),     // OUT
    .CLK_OUT2_100_bus(CLK_OUT2_100_bus),     // OUT
    .CLK_OUT3_200_ref_pll(CLK_OUT3_200_ref_pll),     // OUT
    // Status and control signals
    .RESET(RESET),// IN
    .LOCKED(LOCKED));      // OUT
// INST_TAG_END ------ End INSTANTIATION Template ---------
