## SPI Nets

NET "cat_ce"  LOC = "Y1"    | IOSTANDARD = LVCMOS18;
NET "cat_miso"  LOC = "V1"  | IOSTANDARD = LVCMOS18;
NET "cat_mosi"  LOC = "T4"  | IOSTANDARD = LVCMOS18;
NET "cat_sclk"  LOC = "P7"  | IOSTANDARD = LVCMOS18;

NET "fx3_ce"  LOC = "H20" | IOSTANDARD = LVCMOS18 ;
NET "fx3_miso"  LOC = "G20" | IOSTANDARD = LVCMOS18 ;
NET "fx3_mosi"  LOC = "AA20" | IOSTANDARD = LVCMOS18 ;
#NET "fx3_mosi"  LOC = "A9" | IOSTANDARD = LVCMOS33 ;
NET "fx3_sclk"  LOC = "Y21" | IOSTANDARD = LVCMOS18 ;

NET "pll_ce"  LOC = "W11" | IOSTANDARD = LVCMOS18 ;
NET "pll_mosi"  LOC = "AB11" | IOSTANDARD = LVCMOS18 ;
NET "pll_sclk"  LOC = "Y12" | IOSTANDARD = LVCMOS18 ;

## UART header not always connected so has pullups. Can also be GPIO as build option.
NET "FPGA_RXD0"  LOC = "AB8" | IOSTANDARD = LVCMOS18 | PULLUP ;
NET "FPGA_TXD0"  LOC = "AB7" | IOSTANDARD = LVCMOS18 | PULLUP ;

## Catalina Controls

NET "codec_enable"  LOC = "J6"  | IOSTANDARD = LVCMOS18;
NET "codec_en_agc"  LOC = "P6"  | IOSTANDARD = LVCMOS18;
NET "codec_reset"  LOC = "Y2"  | IOSTANDARD = LVCMOS18;
NET "codec_sync"  LOC = "M3"  | IOSTANDARD = LVCMOS18;
NET "codec_txrx"  LOC = "M7"  | IOSTANDARD = LVCMOS18;

NET "codec_ctrl_in<0>"  LOC = "E3"  | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_in<1>"  LOC = "F2"  | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_in<2>"  LOC = "F1"  | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_in<3>"  LOC = "E1"  | IOSTANDARD = LVCMOS18;

NET "codec_ctrl_out<0>"  LOC = "D1"  | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<1>"  LOC = "C1"  | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<2>"  LOC = "H3"  | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<3>"  LOC = "F3"  | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<4>"  LOC = "P1"  | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<5>"  LOC = "J1"  | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<6>"  LOC = "B1"  | IOSTANDARD = LVCMOS18;
NET "codec_ctrl_out<7>"  LOC = "H2"  | IOSTANDARD = LVCMOS18;

## Catalina Data TX

NET "tx_codec_d<0>"  LOC = "T2"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<1>"  LOC = "R1"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<2>"  LOC = "V2"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<3>"  LOC = "N1"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<4>"  LOC = "V3"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<5>"  LOC = "T1"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<6>"  LOC = "W1"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<7>"  LOC = "U1"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<8>"  LOC = "W3"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<9>"  LOC = "U3"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<10>"  LOC = "P2"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<11>"  LOC = "R3"  | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d*" DRIVE = 2;

## Catalina Data RX

NET "rx_codec_d<0>"  LOC = "M1"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<1>"  LOC = "K1"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<2>"  LOC = "K2"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<3>"  LOC = "G3"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<4>"  LOC = "M2"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<5>"  LOC = "J4"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<6>"  LOC = "L3"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<7>"  LOC = "H1"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<8>"  LOC = "L4"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<9>"  LOC = "G1"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<10>"  LOC = "N3"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d<11>"  LOC = "M4"  | IOSTANDARD = LVCMOS18 ;
NET "rx_codec_d*" DRIVE = 2;

## Catalina Clocks

NET "cat_clkout_fpga"  LOC = "J3"  | IOSTANDARD = LVCMOS18;
NET "codec_data_clk_p"  LOC = "K3"  | IOSTANDARD = LVCMOS18;
NET "codec_fb_clk_p"  LOC = "P3"  | IOSTANDARD = LVCMOS18  | DRIVE = 2 ;
NET "codec_main_clk_p"  LOC = "K5"   | IOSTANDARD = LVDS_25;
NET "codec_main_clk_n"  LOC = "K4"   | IOSTANDARD = LVDS_25;

NET "rx_frame_p"  LOC = "U4"  | IOSTANDARD = LVCMOS18;
NET "tx_frame_p"  LOC = "T3"  | IOSTANDARD = LVCMOS18  | DRIVE = 2 ;

## Debug Bus

NET "debug<0>"  LOC = "D10" | IOSTANDARD = LVCMOS33 ;
NET "debug<1>"  LOC = "D9" | IOSTANDARD = LVCMOS33 ;
NET "debug<2>"  LOC = "A8" | IOSTANDARD = LVCMOS33 ;
NET "debug<3>"  LOC = "B8" | IOSTANDARD = LVCMOS33 ;
NET "debug<4>"  LOC = "C8" | IOSTANDARD = LVCMOS33 ;
NET "debug<5>"  LOC = "D8" | IOSTANDARD = LVCMOS33 ;
NET "debug<6>"  LOC = "A7" | IOSTANDARD = LVCMOS33 ;
NET "debug<7>"  LOC = "D7" | IOSTANDARD = LVCMOS33 ;
NET "debug<8>"  LOC = "A6" | IOSTANDARD = LVCMOS33 ;
NET "debug<9>"  LOC = "B6" | IOSTANDARD = LVCMOS33 ;
NET "debug<10>"  LOC = "C6" | IOSTANDARD = LVCMOS33 ;
NET "debug<11>"  LOC = "D6" | IOSTANDARD = LVCMOS33 ;
NET "debug<12>"  LOC = "A5" | IOSTANDARD = LVCMOS33 ;
NET "debug<13>"  LOC = "A4" | IOSTANDARD = LVCMOS33 ;
NET "debug<14>"  LOC = "C5" | IOSTANDARD = LVCMOS33 ;
NET "debug<15>"  LOC = "A3" | IOSTANDARD = LVCMOS33 ;
NET "debug<16>"  LOC = "A18" | IOSTANDARD = LVCMOS33 ;
NET "debug<17>"  LOC = "B18" | IOSTANDARD = LVCMOS33 ;
NET "debug<18>"  LOC = "A17" | IOSTANDARD = LVCMOS33 ;
NET "debug<19>"  LOC = "C17" | IOSTANDARD = LVCMOS33 ;
NET "debug<20>"  LOC = "C14" | IOSTANDARD = LVCMOS33 ;
NET "debug<21>"  LOC = "D12" | IOSTANDARD = LVCMOS33 ;
NET "debug<22>"  LOC = "C10" | IOSTANDARD = LVCMOS33 ;
NET "debug<23>"  LOC = "F15" | IOSTANDARD = LVCMOS33 ;
NET "debug<24>"  LOC = "E14" | IOSTANDARD = LVCMOS33 ;
NET "debug<25>"  LOC = "F14" | IOSTANDARD = LVCMOS33 ;
NET "debug<26>"  LOC = "H14" | IOSTANDARD = LVCMOS33 ;
NET "debug<27>"  LOC = "D13" | IOSTANDARD = LVCMOS33 ;
NET "debug<28>"  LOC = "F13" | IOSTANDARD = LVCMOS33 ;
NET "debug<29>"  LOC = "G13" | IOSTANDARD = LVCMOS33 ;
NET "debug<30>"  LOC = "E12" | IOSTANDARD = LVCMOS33 ;
NET "debug<31>"  LOC = "H13" | IOSTANDARD = LVCMOS33 ;

NET "debug_clk<0>"  LOC = "A12" | IOSTANDARD = LVCMOS33 ;
NET "debug_clk<1>"  LOC = "C12" | IOSTANDARD = LVCMOS33 ;

NET "debug*" DRIVE = 2;

## GPIF

NET "IFCLK"  LOC = "H21" | IOSTANDARD = LVCMOS18 ;
NET "FX3_EXTINT"  LOC = "U20" | IOSTANDARD = LVCMOS18 ;

NET "IFCLK" DRIVE = 8;
NET "IFCLK" SLEW = SLOW;

NET "GPIF_CTL0"  LOC = "P22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL1"  LOC = "N22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL2"  LOC = "AA18" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL3"  LOC = "AB18" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL4"  LOC = "P19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL5"  LOC = "AA2" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL6"  LOC = "M22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL7"  LOC = "AB19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL8"  LOC = "M19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL9"  LOC = "R20" | IOSTANDARD = LVCMOS18 ;
##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
NET "GPIF_CTL11"  LOC = "M21" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_CTL12"  LOC = "M20" | IOSTANDARD = LVCMOS18 ;

NET "GPIF_D<0>"  LOC = "T17" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<1>"  LOC = "U14" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<2>"  LOC = "U13" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<3>"  LOC = "AA6" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<4>"  LOC = "AB6" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<5>"  LOC = "Y3" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<6>"  LOC = "AB3" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<7>"  LOC = "AA4" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<8>"  LOC = "V20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<9>"  LOC = "AB2" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<10>"  LOC = "V21" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<11>"  LOC = "T22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<12>"  LOC = "U22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<13>"  LOC = "R22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<14>"  LOC = "AA12" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<15>"  LOC = "AB12" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<16>"  LOC = "Y13" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<17>"  LOC = "N20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<18>"  LOC = "T21" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<19>"  LOC = "K18" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<20>"  LOC = "H22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<21>"  LOC = "J20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<22>"  LOC = "K19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<23>"  LOC = "L19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<24>"  LOC = "N19" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<25>"  LOC = "K22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<26>"  LOC = "L22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<27>"  LOC = "L20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<28>"  LOC = "J22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<29>"  LOC = "K20" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<30>"  LOC = "G22" | IOSTANDARD = LVCMOS18 ;
NET "GPIF_D<31>"  LOC = "F22" | IOSTANDARD = LVCMOS18 ;

NET "GPIF_*" DRIVE = 2;
NET "GPIF_*" SLEW = SLOW;

## GPS

NET "gps_lock"  LOC = "B14" | IOSTANDARD = LVCMOS33 ;
NET "gps_rxd"  LOC = "A15" | IOSTANDARD = LVCMOS33 ;
NET "gps_txd"  LOC = "A14" | IOSTANDARD = LVCMOS33  | PULLUP;
NET "gps_txd_nmea"  LOC = "C15" | IOSTANDARD = LVCMOS33 | PULLUP ;

## LEDS

NET "LED_RX1"  LOC = "C22" | IOSTANDARD = LVCMOS18 ;
NET "LED_RX2"  LOC = "L15" | IOSTANDARD = LVCMOS18 ;
NET "LED_TXRX1_TX"  LOC = "C20" | IOSTANDARD = LVCMOS18 ;
NET "LED_TXRX2_RX"  LOC = "D21" | IOSTANDARD = LVCMOS18 ;
NET "LED_TXRX1_RX"  LOC = "K16" | IOSTANDARD = LVCMOS18 ;
NET "LED_TXRX2_TX"  LOC = "D22" | IOSTANDARD = LVCMOS18 ;

## Misc Hardware Control
NET "ref_sel"  LOC = "AA14" | IOSTANDARD = LVCMOS18 ;
NET "pll_lock"  LOC = "AB10" | IOSTANDARD = LVCMOS18 ;
NET "AUX_PWR_ON"  LOC = "B16" | IOSTANDARD = LVCMOS33 ;
#NET "RFUSE"  LOC = "P15" | IOSTANDARD = LVCMOS33 ;

## PPS

NET "PPS_IN_EXT"  LOC = "B10" | IOSTANDARD = LVCMOS33 ;
NET "PPS_IN_INT"  LOC = "A10" | IOSTANDARD = LVCMOS33 ;

## RF Hardware Control

NET "SFDX1_RX"  LOC = "A16" | IOSTANDARD = LVCMOS33 ;
NET "SFDX1_TX"  LOC = "D14" | IOSTANDARD = LVCMOS33 ;
NET "SFDX2_RX"  LOC = "C11" | IOSTANDARD = LVCMOS33 ;
NET "SFDX2_TX"  LOC = "A11" | IOSTANDARD = LVCMOS33 ;
NET "SRX1_RX"  LOC = "D15" | IOSTANDARD = LVCMOS33 ;
NET "SRX1_TX"  LOC = "C16" | IOSTANDARD = LVCMOS33 ;
NET "SRX2_RX"  LOC = "B12" | IOSTANDARD = LVCMOS33 ;
NET "SRX2_TX"  LOC = "D11" | IOSTANDARD = LVCMOS33 ;
NET "tx_bandsel_a"  LOC = "C13" | IOSTANDARD = LVCMOS33 ;
NET "tx_bandsel_b"  LOC = "D17" | IOSTANDARD = LVCMOS33 ;
NET "tx_enable1"  LOC = "Y4" | IOSTANDARD = LVCMOS18 ;
NET "tx_enable2"  LOC = "R19" | IOSTANDARD = LVCMOS18 ;
NET "rx_bandsel_a"  LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "rx_bandsel_b"  LOC = "A13" | IOSTANDARD = LVCMOS33 ;
NET "rx_bandsel_c"  LOC = "E16" | IOSTANDARD = LVCMOS33 ;

## FPGA Config Pins

#NET "FPGA_CFG_INIT_B"  LOC = "T6" | IOSTANDARD = LVCMOS18 ;
#NET "FPGA_CFG_DONE"  LOC = "Y22" | IOSTANDARD = LVCMOS18 ;
#NET "FPGA_CFG_M0"  LOC = "AA22" | IOSTANDARD = LVCMOS18 ;
#NET "FPGA_CFG_M1"  LOC = "U15" | IOSTANDARD = LVCMOS18 ;
#NET "FPGA_CFG_PROG_B"  LOC = "AA1" | IOSTANDARD = LVCMOS18 ;

## Special Pins

#NET "VFS"  LOC = "P16" | IOSTANDARD = LVCMOS33 ;
#NET "TMS"  LOC = "C18" | IOSTANDARD = LVCMOS33 ;
#NET "TDO"  LOC = "A19" | IOSTANDARD = LVCMOS33 ;
#NET "TDI"  LOC = "E18" | IOSTANDARD = LVCMOS33 ;
#NET "TCK"  LOC = "G15" | IOSTANDARD = LVCMOS33 ;
#NET "GND"  LOC = "N15" | IOSTANDARD = LVCMOS33 ;
